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HCS112D Hoja de datos - Intersil

Número de piezaDescripción (Función)Fabricante
HCS112D Radiation Hardened Dual JK Flip-Flop Intersil
Intersil Intersil
Otro PDF  no disponible.
HCS112D Ficha de datos PDF : HCS112D pdf   
HCS112MS image

The Intersil HCS112MS is a Radiation Hardened dual JK flip-flop with set and reset. The output changes state on the negative going transition of the clock pulse. Set and reset are accomplished asynchronously by a logic low input level.
The HCS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS112MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).

• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
    - VIL = 30% of VCC Max
    - VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH


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