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FIN1026 Hoja de datos - Fairchild Semiconductor

Número de piezaDescripción (Función)Fabricante
FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver Fairchild
Fairchild Semiconductor Fairchild
FIN1026 PDF Hoja de datos : FIN1026 pdf   
FIN1026MTC image

General Description
This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data.
The FIN1026 can be paired with its companion driver, the FIN1025, or any other LVDS driver.
   
Features
■ Greater than 400Mbs data rate
■ Flow-through pinout simplifies PCB layout
■ 3.3V power supply operation
■ 0.4ns maximum differential pulse skew
■ 2.5ns maximum propagation delay
■ Low power dissipation
■ Power-Off protection
■ Fail safe protection for open-circuit, shorted and
    terminated non-driven input conditions
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ 14-Lead TSSOP package saves space
   

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