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ISB35832 Hoja de datos - STMicroelectronics

Número de piezaDescripción (Función)Fabricante
ISB35832 HCMOS STRUCTURED ARRAY ST-Microelectronics
STMicroelectronics ST-Microelectronics
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ISB35832 Ficha de datos PDF : ISB35832 pdf   
ISB35000 image

GENERAL DESCRIPTION
The ISB35000 array series uses a high performance, low voltage, triple level metal, HCMOS 0.5 micron process to achieve sub-nanosecond internal speeds while offering very low power dissipation and high noise immunity. The potential total gate count ranges above 1 million equivalent usable gates. The array operates over a Vdd voltage range of 2.7 to 3.6 volts.
The I/O count for this array family ranges to over 600 signals and 1000 pins dependent upon the package technology utilized. A Sea of I/O approach has been followed to give a solution to today’s problems of drive levels and specialized interface standards. The array does not utilize a set bond pad spacing but allows for pad spacings from 80 microns upwards.
The I/O can be configured for circuits ranging from low voltage CMOS and TTL to 200 mHz plus low swing differential circuits. Standards like GTL, SCSI-2, 3.3 Volt PCI, CTI, and a limited set of 5.0 Volt interfaces are currently being addressed. A specialized set of impedance matched transmis sion line driver LVTTL type circuits are also avail able with 25, 35, 45, and 55 Ohm output impedance. These buffers sacrifice direct current capabilities for matching positive and negative volt age and current waveforms.

FEATURES
■ 0.5 micron triple layer metal HCMOS process
   featuring retrograde well technology, low
   resistance salicided active areas, polysilicide
   gates and thin metal oxide.
■ 3.3 V optimized transistor with 5 V I/O interface capability
■ 2 - input NAND delay of 0.210 ns (typ) with fanout = 2.
■ Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS.
■ High drive I/O; capability of sinking up to 48 mA
   with slew rate control, current spike suppression and impedance matching.
■ Metallised generators to support SPRAM and
   DPRAM, plus an extensive embedded function library.
■ Combines Standard Cell Features with Sea of Gates time to market.
■ Fully independent power and ground configurations for inputs, core and outputs.
■ Programmable I/O ring capability up to 1000 pads.
■ Output buffers capable of driving ISA, EISA, PCI, MCA, and SCSI interface levels.
■ Active pull up and pull down devices.
■ Buskeeper I/O functions.
■ Oscillators for wide frequency spectrum.
■ Broad range of 400 SSI cells.
■ 300 element macrofunction library.
■ Design For Test includes LSSD macro library option and IEEE 1149.1
   JTAG Boundary Scan architecture built in.
■ Cadence and Mentor based design system with
   interfaces from multiple workstations.
■ Broad ceramic and plastic package range.
■ Latchup trigger current +/- 500 mA. ESD protection +/- 4000 volts.

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