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BA6129AF

Reset IC with battery backup function

ROHM Semiconductor 

Memory ICs

BA6129AF / BA6162 / BA6162F

•Circuit operation

These ICs have two distinct functions, a logic output function and a power supply switching function.

The logic output circuit consists of the following:

(1) Reset output (NPN Tr open collector)

(2) CS output (PNP Tr open collector + pull-down resistor)

(3) CSB output (NPN Tr open collector + pull-up resistor)

The power supply switching circuit consists of a PNP

power transistor and an SBD (Schottky barrier diode).

The normal power supply VCC and the battery backup

power supply (VBAT) are both connected to the switch-

ing circuit. When the PNP power transistor is turned on

and off, the IC power is switched from the normal

power supply to the battery backup power supply, and

vice versa.

The power supply voltage detection circuit consists of a

standard voltage source VREF and a hysteresis com-

parator. The power supply VCC is detected using a split

resistance. When the power supply voltage drops

below the detection voltage (BA6129AF: VS = 3.5Vtyp.

when VCC drops and VS + 0.1Vtyp. when VCC rises;

BA6162 / F: VS = 4.2Vtyp. when VCC drops, and VS +

0.1Vtyp. when VCC rises), the Reset signal (Low) and

the CS signal (CS-Low, CSB-High) are output by the

logic output function, and the SRAM (or other memory

device) is switched to backup mode.

If the power supply VCC drops further and goes below

the switching voltage (BA6129AF and BA6162 / F: VB =

3.3Vtyp. when VCC drops, VB + 0.1Vtyp. when VCC

rises), the SBD develops a forward bias because the

PNP power transistor is off. The power supply output

VO switches from the power supply VCC to the battery

power supply (VBAT).

When the normal power supply VCC rises, the above

process is reversed.

(BA6129AF) (BA6162 / F)

VCC

5V

VS [3.5VTyp.] [4.2VTyp.]

VB [3.3VTyp.]

OV

VO (Vcc) [5V—VSAT1]

VO

VO (BAT) [3V—VSAT2]

RESET

OV

VRESH [Լ VCC]

VRESL [Լ GND]

VCSH [Լ VCC]

CS

CSB

VCSL [Լ GND]

VCSBH [Լ VO]

VCSBL [Լ GND]

Fig. 2 Timing chart

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