W83194BR-39B Ver la hoja de datos (PDF) - Winbond
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W83194BR-39B Datasheet PDF : 20 Pages
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W83194BR-39B
PRELIMINARY
7.2 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the default state at
true power up. "Command Code" byte and "Byte Count" byte must be sent following the
acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't
care", they must be sent and will be acknowledge. After that, the sequence described below
(Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
FREQUENCY BY SOFTWARE
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0
00 0 0 0 0
00 0 0 0 1
00 0 0 1 0
00 0 0 1 1
00 0 1 0 0
00 0 1 0 1
00 0 1 1 0
00 0 1 1 1
00 1 0 0 0
00 1 0 0 1
00 1 0 1 0
00 1 0 1 1
00 1 1 0 0
00 1 1 0 1
00 1 1 1 0
00 1 1 1 1
01 0 0 0 0
01 0 0 0 1
01 0 0 1 0
01 0 0 1 1
01 0 1 0 0
01 0 1 0 1
01 0 1 1 0
01 0 1 1 1
01 1 0 0 0
01 1 0 0 1
01 1 0 1 0
CPU(MHz)
80.00
75.00
83.30
66.82
103.00
112.00
68.01
100.23
120.00
115.00
120.00
105.00
140.00
155.00
124.00
133.30
160.00
127.00
130.00
135.00
136.00
137.00
139.00
140.00
141.00
142.00
143.00
SDRAM(MHz)
80.00
75.00
83.30
66.82
103.00
112.00
68.01
100.23
120.00
115.00
120.00
105.00
140.00
155.00
124.00
133.30
160.00
127.00
130.00
135.00
136.00
137.00
139.00
140.00
141.00
142.00
143.00
PCI(MHz)
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
30.00
38.33
40.00
35.00
35.00
38.75
31.00
33.30
40.00
31.75
32.50
33.75
34.00
34.25
34.75
35.00
35.25
35.50
35.75
Publication Release Date: June 2000
-7-
Revision 0.46
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