MA5104 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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MA5104

RADIATION HARD 4096 x 1 BIT STATIC RAM

Zarlink Semiconductor Inc 

MA5104

TAVAVW

ADDRESS

TAVWL

TAVWH

TWLWH (2)

TWHAV (3)

WE

DATA OUT

HIGH

IMPEDANCE

(4)

TELWL

(7)

TWLQZ

DATA IN

TAXQX

TWLQH

(5)

(6)

TDVWH

DATA VALID

TWHDX

TELWH

CS

1. WE must be high during all address transitions.

2. A write occurs during the overlap (TWLWH) of a low CS, a high CE and a low WE.

3. TWHAV is measured from either CS or WE going high or CE going low, whichever is the earlier, to the end

of the write cycle.

4. If the CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in

the high impedance state.

5. DATA OUT is the write data of the current cycle, if selected.

6. DATA OUT is the read data of the next address,if selected.

7. TELWL must be met to prevent memory corruption.

Figure 12: Write Cycle

6

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