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74AHC573 Datasheet PDF : 19 Pages
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NXP Semiconductors
74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
5. Pinning information
5.1 Pinning
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
573
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
001aad099
Fig 5. Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2. Pin description
Symbol
Pin
OE
1
D0 to D7
2, 3, 4, 5, 6, 7, 8, 9
GND
10
LE
11
Q0 to Q7
19, 18, 17, 16, 15, 14, 13, 12
VCC
20
terminal 1
index area
74AHC573
74AHCT573
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND(1)
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
001aal532
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration DHVQFN20
Description
output enable input (active LOW)
data input
ground (0 V)
latch enable (active HIGH)
data output
supply voltage
74AHC_AHCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 25 November 2010
© NXP B.V. 2010. All rights reserved.
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