PEB20542 Ver la hoja de datos (PDF) - Infineon Technologies

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PEB20542

2 Channel Serial Optimized Communication Controller with DMA

Infineon Technologies 

PEB 20542

Revision History:

Previous Version:

Page

(previous

Version)

Page

(current

Version)

34-36

36-38

85

87

218, 226 222, 230

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-

268

272

2000-09-14

DS 1

MISTRAL V1.1 Preliminary Data Sheet, 08.99, DS1

Subjects (major changes since last revision)

Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal

’OST’ is multiplexed with ’CTS’ (was vice versa)

corrected HDLC receive address recognition table

Corrected location of TCD interrupt (async/bisync modes only)

in registers ISR0 and IMR0 from bit 7 to bit 2.

removed referneces to Intel Multiplexed Mode

Chapter "Electrical Characteristics" updated with final

characterization results.

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Technologies Offices in Germany or the Infineon Technologies Companies and

Representatives worldwide: see our webpage at http://www.infineon.com

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