SL74HC175 Ver la hoja de datos (PDF) - System Logic Semiconductor
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SL74HC175 Datasheet PDF : 5 Pages
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SL74HC175
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
tPHL, tPLH Maximum Propagation Delay , Reset to Q or Q
(Figures 2 and 4)
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
CIN
Maximum Input Capacitance
VCC
Guaranteed Limit
V 25 °C to ≤85°C ≤125°C Unit
-55°C
2.0 6.0
4.8
4.0 MHz
4.5 30
24
20
6.0 35
28
24
2.0 150
190
225
ns
4.5 30
38
45
6.0 26
33
38
2.0 125
155
190
ns
4.5 25
31
38
6.0 21
26
32
2.0 75
95
110
ns
4.5 15
19
22
6.0 13
16
19
-
10
10
10
pF
Power Dissipation Capacitance (Per Flip-Flop)
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
35
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V
25 °C to
≤85°C
≤125°C
Unit
-55°C
tSU
Minimum Setup Time, Data to 2.0
100
125
150
ns
Clock (Figure 3)
4.5
20
25
30
6.0
17
21
26
th
Minimum Hold Time, Clock to 2.0
3
3
3
ns
Data (Figure 3)
4.5
3
3
3
6.0
3
3
3
trec
Minimum Recovery Time,
2.0
100
125
150
ns
Reset Inactive to Clock (Figure 4.5
20
25
30
2)
6.0
17
21
26
tw
Minimum Pulse Width, Clock
2.0
80
(Figure 1)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tw
Minimum Pulse Width, Reset
2.0
80
(Figure 2)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tr, tf Maximum Input Rise and Fall
2.0
1000
1000
1000
ns
Times (Figure 1)
4.5
500
500
500
6.0
400
400
400
SLS
System Logic
Semiconductor
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