TC58NVG0S3AFT05 Ver la hoja de datos (PDF) - Toshiba

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TC58NVG0S3AFT05

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Toshiba 

TC58NVG0S3AFT05

(10) Note regarding the WP signal

The Erase and Program operations are automatically reset when WP goes Low. The operations are

enabled and disabled as follows:

Enable Programming

WE

DIN

80

10

WP

RY/BY

tWW (100 ns min)

Disable Programming

WE

DIN

80

10

WP

RY/BY

tWW (100 ns min)

Enable Erasing

WE

DIN

60

D0

WP

RY/BY

tWW (100 ns min)

Disable Erasing

WE

DIN

60

D0

WP

RY/BY

tWW (100 ns min)

2003-08-20A 27/33

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