SM8702AM
24MHz/48MHz, REF[0:1] clock characteristics
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 20pF unless otherwise noted.
Parameter
Symbol
Condition
Rating
Unit
min
typ
max
Output clock rise time1
Output clock fall time1
Duty cycle1
Output clock jitter1
tr
VOL = 0.8V → VOH = 2.4V transition time
tf
VOH = 2.4V → VOL = 0.8V transition time
Dt VT = 1.5V
tjc V T = 1.5V, rising edge Absolute jitter
–
–
2.0
ns
–
–
2.0
ns
40
50
60
%
–
250
800
ps
Clock frequency stabilize time1
tstb Cold start
Supply ON (VDD = 3.3V)
until clock reaches
–
–
3
ms
specified frequency
Output impedance2
ZO
VO = 0.5VDD
10
–
60
Ω
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
IOAPIC clock characteristics
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 20pF unless otherwise noted.
Parameter
Symbol
Condition
Rating
Unit
min
typ
max
Output clock rise time1
VOL = 0.8V → VOH = 2.4V transition time,
VDDL1 = 3.3V
tr
VOL = 0.4V → VOH = 2.0V transition time,
VDDL1 = 2.5V
–
–
2.0
ns
–
–
2.0
Output clock fall time1
Duty cycle1
Output clock jitter1
VOH = 2.4V → VOL = 0.8V transition time,
VDDL1 = 3.3V
tf
VOH = 2.0V → VOL = 0.4V transition time,
VDDL1 = 2.5V
Dt V T = 1.5V, V D D L 1 = 3.3V
tjc V T = 1.5V, rising edge Absolute jitter
–
–
2.0
ns
–
–
2.0
40
50
60
%
–
250
800
ps
Clock frequency stabilize time1
tstb Cold start
Supply ON (VDD = 3.3V)
until clock reaches
–
–
3
ms
specified frequency
Output impedance2
ZO
VO = 0.5VDD
10
–
90
Ω
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—9