TC58256AFTI Ver la hoja de datos (PDF) - Toshiba

Número de pieza

componentes Descripción

Lista de partido

TC58256AFTI

256-MBIT (32M X 8 BITS) CMOS NAND E2PROM

Toshiba 

TC58256AFTI

Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.

(Refer to Application Note (9) toward the end of this document.)

(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay

is less than 30 ns, RY/BY signal stays Ready.

tCEH ≥ 100 ns

*

*: VIH or VIL

CE

RE

525

526

527

A

A : 0 to 30 ns → Busy signal is not output.

RY/BY

Busy

tCRY

PROGRAMMING AND ERASING CHARACTERISTICS (Ta = - 40° to 85°C, VCC = 2.7 V to 3.6 V)

SYMBOL

PARAMETER

MIN

tPROG

N

Programming Time



Number of Programming Cycles on Same

Page



tBERASE

Block Erasing Time



(1): Refer to Application Note (12) toward the end of this document.

TYP.

200 to 300



2

MAX

1000

3

10

UNIT

µs

ms

NOTES

(1)

2001-05-30 5/33

Share Link: