CS4954-CQ Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza

componentes Descripción

Lista de partido

CS4954-CQ

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4954 CS4955

can be varied via the U_AMP and V_AMP 8-bit

host addressable registers.

The U and V chroma signals are fed to a quadrature

modulator in which they are combined with the

output from the subcarrier synthesizer to produce

the proper modulated chrominance signal.

The chroma then is interpolated by a factor of two

in order to operate the output DACs at twice the

pixel rate. The interpolated filters enable running

the DACs at twice the pixel rate and this helps re-

duce the sinx/x roll-off for higher frequencies and

reduces the complexity of the external analog low

pass filters.

4.5. Luma Path

Along with the chroma output path, the CS4954/5

Video Input Formatter initiates a parallel luma data

path by directing the luma data to a digital delay

line. The delay line is built as a digital FIFO in

which the depth of the FIFO replicates the clock

period delay associated with the more complex

chroma path. Brightness adjustment is also provid-

ed via the 8-bit BRIGHTNESS_OFFSET Register.

Following the luma delay, the data is passed

through an interpolation filter that has a program-

mable bandwidth, followed by a variable gain am-

plifier in which the luma DC values are modifiable

via the Y_AMP Register.

The output of the luma amplifier connects to the

sync insertion block. Sync insertion is accom-

plished by multiplexing, into the luma data path,

the different sync DC values at the appropriate

times. The digital sync generator takes horizontal

sync and vertical sync timing signals and generates

the appropriate composite sync timing (including

vertical equalization and serration pulses), blank-

ing information, and burst flag. The sync edge rates

conform to RS-170A or ITU R.BT601 and ITU

R.BT470 specifications.

It is also possible to delay the luminance signal,

with respect to the chrominance signal, by up to

three pixel clocks. This variable delay is useful to

offset different propagation delays of the luma

baseband and modulated chroma signals. This ad-

justable luma delay is available only on the

CVBS_1 output.

4.6. RGB Path and Component YUV Path

The RGB datapath has the same latency as the luma

and chroma path. Therefore all six simultaneous

analog outputs are synchronized. The 4:2:2 YCbCr

data is first interpolated to 4:4:4 and then interpo-

lated to 27 MHz. The color space conversion is per-

formed at 27 MHz. The coefficients for the color

space conversion conform to the ITU R.BT601

specifications.

After color space conversion, the amplitude of each

component can be independently adjusted via the

R_AMP, G_AMP, and B_AMP 8-bit host address-

able registers. A synchronization signal can be add-

ed to either one, two or all of the RGB signals. The

synchronization signal conforms to NTSC or PAL

specifications.

Some applications (e.g., projection TVs) require

analog component YUV signals. The chip provides

a programmable mode that outputs component

YUV data. Sync can be added to the luminance sig-

nal. Independent gain adjustment of the three com-

ponents is provided as well.

4.7. Digital to Analog Converters

The CS4954/5 provides six discrete 27 MHz DACs

for analog video. The default configuration is one

10-bit DAC for S-video chrominance, one 10-bit

DAC for S-Video luminance, one 10-bit DAC for

composite output, and three 10-bit DACs for RGB

outputs. All six DACs are designed for driving ei-

ther low-impedance loads (double terminated

75 Ω) or high-impedance loads (double terminated

300 Ω). There are five different DAC configura-

tions to choose from (see Table 1, below).

The DACs can be put into tri-state mode via host-

addressable control register bits. Each of the six

12

DS278PP4

Share Link: