74F646 Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Lista de partido
74F646 Datasheet PDF : 9 Pages
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Unit Loading/Fan Out
Pin Names
A0–A7
B0–B7
CPAB, CPBA
SAB, SBA
G
DIR
Description
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
U.L.
HIGH/LOW
3.5/1.083
600/106.6 (80)
3.5/1.083
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
Input IIH/IIL
Output IOH/IOL
70 µA/−650 µA
−12 mA/64 mA (48 mA)
70 µA/−650 µA
−12 mA/64 mA (48 mA)
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Function Table
Inputs
Data I/O (Note 1)
G DIR CPAB CPBA SAB SBA A0–A7 B0–B7
Function
H
H
H
X
X
X
H or L H or L
X
X
X
X
X
X
Isolation
X
Input Input Clock An Data into A Register
X
Clock Bn Data into B Register
L
L
H
H
X
X
X
L
L
X
An to Bn—Real Time (Transparent Mode)
X
Input Output Clock An Data into A Register
L
L
H H or L X
H
X
H
H
X
X
A Register to Bn (Stored Mode)
Clock An Data into A Register and Output to Bn
L
L
L
L
X
X
X
X
X
L
L
L
L
X H or L X
X
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Irrelevant
= LOW-to-HIGH Transition
L
Bn to An—Real Time (Transparent Mode)
L Output Input Clock Bn Data into B Register
H
B Register to An (Stored Mode)
H
Clock Bn Data into B Register and Output to An
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
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