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M74HCT533

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT INVERTING

STMicroelectronics 

M74HCT533

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUT INVERTING

s HIGH SPEED:

tPD =20ns (TYP.) at VCC = 4.5V

s LOW POWER DISSIPATION:

ICC = 4µA(MAX.) at TA=25°C

s COMPATIBLE WITH TTL OUTPUTS :

VIH = 2V (MIN.) VIL = 0.8V (MAX)

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 6mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 533

DESCRIPTION

The M74HCT533 is an high speed CMOS OCTAL

LATCH WITH 3-STATE OUTPUTS fabricated

with silicon gate C2MOS technology.

This 8-BIT D-Type latches is controlled by a latch

enable input (LE) and output enable input (OE).

While the LE input is held at a high level, the Q

outputs will follow the data input inversely. When

LE is taken low, the Q outputs will be latched

inversely at the logic level of D input data.

While the OE input is at low level, the eight outputs

will be in a normal logic state (high or low logic

DIP

SOP

TSSOP

ORDER CODES

PACKAGE

TUBE

T&R

DIP

SOP

TSSOP

M74HCT533B1R

M74HCT533M1R M74HCT533RM13TR

M74HCT533TTR

level) and while high level the outputs will be in a

high impedance state.

The 3-State output configuration and the wide

choice of outline make bus organized system

simple.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

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