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CS61880-IB

Octal E1 Line Interface Unit

Cirrus Logic 

CS61880

LIST OF FIGURES

Figure 1. CS61880 144-Pin LQFP Package Pin Outs .................................................................... 7

Figure 2. CS61880 160-Ball FBGA Package Pin Outs ................................................................... 8

Figure 3. G.703 BITS Clock Mode in NRZ Mode .......................................................................... 23

Figure 4. G.703 BITS Clock Mode in RZ Mode............................................................................. 23

Figure 5. G.703 BITS Clock Mode in Remote Loopback .............................................................. 23

Figure 6. Pulse Mask at E1 Interface ........................................................................................... 24

Figure 7. Analog Loopback Block Diagram................................................................................... 30

Figure 8. Analog Loopback with TAOS Block Diagram................................................................. 30

Figure 9. Digital Loopback Block Diagram .................................................................................... 31

Figure 10. Digital Loopback with TAOS ........................................................................................ 31

Figure 11. Remote Loopback Block Diagram ............................................................................... 31

Figure 12. Serial Read/Write Format (SPOL = 0) ......................................................................... 33

Figure 13. Arbitrary Waveform UI ................................................................................................. 42

Figure 14. Test Access Port Architecture...................................................................................... 44

Figure 15. TAP Controller State Diagram ..................................................................................... 45

Figure 16. Internal RX/TX Impedance Matching ........................................................................... 50

Figure 17. Internal TX, External RX Impedance Matching............................................................ 51

Figure 18. Jitter Transfer Characteristic vs. G.736 & TBR 12/13.................................................. 56

Figure 19. Jitter Tolerance Characteristic vs. G.823..................................................................... 57

Figure 20. Recovered Clock and Data Switching Characteristics................................................. 59

Figure 21. Transmit Clock and Data Switching Characteristics .................................................... 59

Figure 22. Signal Rise and Fall Characteristics ............................................................................ 59

Figure 23. Serial Port Read Timing Diagram ................................................................................ 60

Figure 24. Serial Port Write Timing Diagram ................................................................................ 60

Figure 25. Parallel Port Timing - Write; Intel Multiplexed Address / Data Bus Mode .................... 62

Figure 27. Parallel Mode Port Timing - Read; Intel Multiplexed Address / Data Bus Mode......... 62

Figure 26. Parallel Port Timing - Write; Motorola Multiplexed Address / Data Bus Mode............. 63

Figure 28. Parallel Port Timing - Read; Motorola Multiplexed Address / Data Bus Mode............. 63

Figure 29. Parallel Port Timing - Read; Intel Non-Multiplexed Address / Data Bus Mode ............ 65

Figure 30. Parallel Port Timing - Write; Intel Non-Multiplexed Address / Data Bus Mode ............ 65

Figure 31. Parallel Port Timing - Read; Motorola Non-Multiplexed Address / Data Bus Mode..... 66

Figure 32. Parallel Port Timing - Write; Motorola Non-Multiplexed Address / Data Bus Mode ..... 66

Figure 33. JTAG Switching Characteristics................................................................................... 67

Figure 34. 160-Ball FBGA Package Drawing................................................................................ 69

Figure 35. 144-Pin LQFP Package Drawing ................................................................................. 70

DS450PP2

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