SAA7110 Ver la hoja de datos (PDF) - Philips Electronics
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componentes Descripción
Lista de partido
SAA7110 Datasheet PDF : 76 Pages
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Philips Semiconductors
One Chip Front-end 1 (OCF1)
Product specification
SAA7110; SAA7110A
8 PINNING
SYMBOL PIN
SP
1
AP
2
RTCO
3
SA
4
SDA
5
SCL
6
i.c.
7
i.c.
8
i.c.
9
VSSA4
10
AI42
11
VDDA4
12
AI41
13
VSSA3
14
AI32
15
VDDA3
16
AI31
17
VSSA2
18
AI22
19
VDDA2
20
AI21
21
VSS(S)
22
AOUT
23
VDDA0
24
VSSA0
25
LFCO
26
VDD
27
VSS
28
LLC
29
LLC2
30
CREF
31
DESCRIPTION
test pin input; (shift pin) connect to ground for normal operation
test pin input; (action pin) connect to ground for normal operation
Real Time Control Output. This pin is used to fit serially the increments of the HPLL and
FSC-PLL and information of the PAL or SECAM sequence.
I2C-bus slave address select input. LOW: slave address = 9CH for write, 9DH for read;
HIGH = 9DH for write, 9FH for read.
I2C-bus serial data input/output
I2C-bus serial clock input
reserved pin; do not connect
reserved pin; do not connect
reserved pin; do not connect
ground for analog input 4
analog input 42
supply voltage (+5 V) for analog input 4
analog input 41
ground for analog input 3
analog input 32
supply voltage (+5 V) for analog input 3
analog input 31
ground for analog input 2
analog input 22
supply voltage (+5 V) for analog input 2
analog input 21
substrate ground
analog test output; do not connect
supply voltage (+5 V) for internal CGC (Clock Generation Circuit)
ground for internal CGC
Line Frequency Control output; this is the analog clock control signal driving the external
CGC. The frequency is a multiple of the actual line frequency (nominally 7.375/6.13636 MHz).
The signal has a triangular form with 4-bit accuracy.
supply voltage (+5 V)
ground
Line-Locked Clock input/output (CGCE = 1, output; CGCE = 0, input). This is the system
clock, its frequency is 1888 × fh for 50 Hz/625 lines per field systems and 1560 × fh for
60 Hz/525 lines per field systems; or variable input clock up to 32 MHz in input mode.
Line-Locked Clock 1⁄2 output; fLLC2 = 0.5 × fLLC (CGCE = 1, output; CGCE = 0, high
impedance).
Clock reference input/output (CGCE = 1, output; CGCE = 0, input). This is a clock qualifier
signal distributed by the internal or an external clock generator circuit (CGC). Using CREF all
interfaces on the YUV-bus are able to generate a bus timing with identical phase.
1995 Oct 18
6
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