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HT9480

8-Bit Numerical Pager Controller MCU

Holtek Semiconductor 

HT9480

Of the four functional groups, the special function regis-

ters of bank 0 consist of an indirect addressing registers

(IAR0;00H, IAR1;02H), memory pointer registers

(MP0;01H, MP1;03H), a memory bank pointer register

(BP;04H), an accumulator (ACC;05H), a program coun-

ter low byte register (PCL;06H), a table pointer

(TBLP;07H), a table high-order part register

(TBLH;08H), a Watchdog Timer option setting register

(WDTS;09H), a status register (STATUS;0AH), an inter-

rupt control register (INTC;0BH), a programmable timer

counter (TMR0;0DH), a programmable timer counter

control register (TMRC0;0EH), a timer/event counter

(TMR1;10H), a timer/event counter control register

(TMRC1;11H), an input port, two I/O ports (PA;12H,

PB;14H, PC;16H), two I/O control register (PBC;15H,

PCC;17H), a tone control register (1DH), a pager con-

trol register (1EH), and a pager data register (1FH). The

special function registers are located from 00H to 1FH

whereas the 32 global data registers are from 20H to

3FH, where each bank points to the same location. The

other spaces, namely 0CH, 0FH, 13H, the high nibble of

16H, 17H, and 18H~1CH, are all reserved for future ex-

pansion usage; reading these locations will get an

²00H² value.

On the other hand, the general purpose data memory,

divided into three banks (bank 0, bank 1, and bank 27),

is used for data, control information, and LCD display

control under instruction commands. The banks in the

RAM are all addressed from 40H to FFH, and are se-

lected by setting the value (²00H²: bank 0; ²01H²: bank

1; ²1BH²: bank 27) of the bank pointer (BP;04H). The

bank27 memory is used for LCD display mapping and

the decoder configuration RAM mapping. The spaces

from 4FH to BFH and from E3H to FFH, and the high

nibble part from C0H to E2H in bank 27 are all reserved

for future expansion usage; reading these locations will

derive ²00H².

The special registers, global data registers and general

data memory can directly perform arithmetic, logic, in-

crement, decrement, and rotate operations. Each bit in

the RAM can be set and reset by ²SET [m].i² and ²CLR

[m].i², and can also be indirectly accessible through the

memory pointer registers (MP0;01H, MP1;03H).

Of the special addresses, 1DH and 1FH cannot directly

do all these operations, because they are not read and

write accessible addresses. 1DH is a write-only ad-

dress, 1FH a read-only address, but these two ad-

dresses namely, 1DH and 1FH can only perform

operations by using the ²MOV² instruction.

Indirect addressing register

IARx (IAR0;00H, IAR1;02H) are indirect address regis-

ters that are not physically implemented. Any read/write

operation of the IARx accesses the data memory

pointed to by MPx (MP0;01H, MP1;03H). Reading the

indirect addressing register itself will indirectly derive

00H, while writing the indirect addressing register indi-

rectly will lead to no operations. (IAR0, MP0) is indirectly

addressable in bank 0, but (IAR1, MP1) is available for

all banks.

Accumulator - ACC

The accumulator (ACC) relates to the ALU operations. It is

also mapped to location 05H of the data memory and is ca-

pable of carrying out immediate data operations. Data

movement between these two data memories has to pass

through the ACC.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic opera-

tions, and provides the following functions:

· Arithmetic operation (ADD, ADC, SUB, SBC, DAA)

· Logic operation (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ, etc.)

The ALU not only saves the results of data operation,

but also changes the contents of the status register.

Status register - STATUS

The status register (0AH) is 8-bit wide. It contains a zero

flag (Z), a carry flag (C), an auxiliary carry flag (AC), an

overflow flag (OV), a powerdown flag (PD), and a WDT

time-out flag (TO). The status register not only records the

status information, but also controls the operation se-

quence.

The status register, like most other registers, can be al-

tered by instructions except for the TO and PD flags.

Any data written into the status register will not change

TO or PD. It should be noted that operations related to

the status register may derive different results from

those intended. For example, clearing the status regis-

ter CLR [0AH] has no effect on the TO and PD flags, and

the value of the zero flag is also ²1², i.e., UU0100 is the

data in the register, where the value of U is an un-

changed value.

The Z, OV, AC, and C flags generally reflect the status of

the latest operations.

On entering an interrupt sequence or executing a sub-

routine call, the status register will not be automatically

pushed onto the stack. If the contents of the status is im-

portant, and if the subroutine may corrupt the status reg-

ister, the programmer should take precautions to save it

properly.

Rev. 1.20

9

July 31, 2002

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