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FUSION878A

PCI Video Decoder

Conexant Systems 

Fusion 878A

PCI Video Decoder

1.0 Product Overview

1.3 Pin Descriptions

Table 1-2. Pin Descriptions Grouped by Pin Function (1 of 4)

Pin #

Pin Name I/O

Signal

Description

PCI Interface (50 Pins) (1)

40

CLK

I Clock

This input provides timing for all PCI transactions. All PCI

signals except RST and INTA are sampled on the rising edge of

CLK, and all other timing parameters are defined with respect to

this edge. The Fusion 878A supports a PCI clock of up to

33.3333 MHz.

127

RST

I Reset

This input three-states all PCI signals asynchronous to the CLK

signal.

3

REQ

O Request

Agent desires bus.

2

GNT

I Grant

Agent granted bus.

13

IDSEL

I Initialization

This input is used to select the Fusion 878A during

Device Select

configuration read and write transactions.

4–11,

14–18,

21–23,

34–37,

41–44,

46–53

AD[31:0]

I/O Address/Data

These three-state, bidirectional I/O pins transfer both address

and data information. A bus transaction consists of an address

phase followed by one or more data phases for either read or

write operations.

The address phase is the clock cycle in which FRAME is first

asserted. During the address phase, AD[31:0] contains a byte

address for I/O operations and a DWORD address for

configuration and memory operations. During data phases,

AD[7:0] contains the least significant byte and AD[31:24]

contains the most significant byte.

Read data is stable and valid when TRDY is asserted and

write data is stable and valid when IRDY is asserted. Data is

transferred during the clocks when both TRDY and IRDY are

asserted.

12, 24,

33, 45

CBE[3:0]

I/O Bus

Command/Byte

Enable

These three-state, bidirectional I/O pins transfer both bus

command and byte enable information. During the address

phase of a transaction, CBE[3:0] signals contain the bus

command. During the data phase, CBE[3:0] are used as byte

enables. The byte enables are valid for the entire data phase and

determine which byte lanes carry meaningful data. CBE[3]

refers to the most significant byte and CBE[0] refers to the least

significant byte.

32

PAR

I/O Parity

This three-state, bidirectional I/O pin provides even parity

across AD[31:0] and CBE[3:0]. This means that the number of

1s on PAR, AD[31:0], and CBE[3:0] equals an even number.

PAR is stable and valid one clock after the address phase. For

data phases, PAR is stable and valid one clock after either TRDY

is asserted on a read, or IRDY is asserted on a write. Once valid,

PAR remains valid until one clock after the completion of the

current data phase. PAR and AD[31:0] have the same timing,

but PAR is delayed by one clock. The target drives PAR for read

data phases; the master drives PAR for address and write data

phases.

100600B

Conexant

1-9

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