RF2460 Ver la hoja de datos (PDF) - RF Micro Devices
Número de pieza
componentes Descripción
Lista de partido
RF2460 Datasheet PDF : 20 Pages
| |||
RF2460
Preliminary
Pin Function Description
Interface Schematic
1
ENABLE Power down pin. A logic “low” turns the part off. A logic “high” (>1.6V)
turns the part on.
2
VCC1
Supply Voltage for the LNA, mixer, bias, and logic circuitry. External RF See pin 20.
and IF bypassing is required. The trace length between the pin and the
bypass capacitors should be minimized. The ground side of the bypass
capacitors should connect immediately to ground plane.
3
VCC2
Supply Voltage for the LO buffer amplifier. External RF and IF bypass-
ing is required. The trace length between the pin and the bypass
capacitors should be minimized. The ground side of the bypass capaci-
tors should connect immediately to ground plane.
4
LO IN
Mixer LO Input Pin.
5
NC
No connection. For isolation purposes, this pin is connected to the
ground plane.
6
NC
No connection. For isolation purposes, this pin is connected to the
ground plane.
7
IF+
CDMA IF Output pin. This is a balanced output. The internal circuitry, in
conjunction with an external matching/bias inductor to VCC, sets the
IF1+ GND2 IF1-
operating impedance. This inductor is typically incorporated in the
matching network between the output and IF filter. The part is designed
1.2 pF 1.2 pF
to drive a 1kΩ load. Because this pin is biased to VCC, a DC blocking
capacitor must be used if the IF filter input has a DC path to ground.
See Application Schematic.
8
8
9
NC
No connection. For isolation purposes, this pin is connected to the
ground plane.
IF-
Same as pin 7, except complementary output.
See pin 6.
10
NC
No connection. For isolation purposes, this pin is connected to the
ground plane.
11
LNA2 E Emitter for LNA2. Increasing the inductance on this pin will reduce the
mixer gain, increase IP3 and noise figure.
12
MIX IN
Mixer RF Input Pin. This pin is internally DC biased and should be DC
blocked if connected to a device with DC present. External matching
network sets RF and IF impedance for optimum performance.
MIX IN
13
ISET2
This pin is used to set the bias current and IIP3 of the mixer amplifier
using a resistor to ground. See plots for values and current settings.
14
ISET1
This pin is used to set the bias current and IIP3 of the LNA amplifier
using a resistor to ground. See plots for values and current settings.
15
LNA OUT LNA output pin. Open collector.
See pin 20.
16
MIX GAIN CMOS compatible signal controlling mixer gain mode. Setting this sig-
nal high places the mixer in the high gain mode. Setting this signal low
places the mixer in low gain mode by bypassing and shutting off the
mixer buffer amplifier current.
MIX GAIN
17
LNA GAIN CMOS compatible signal controlling LNA gain mode. Setting this signal
high places the LNA in the high gain mode. Setting this signal low
bypasses the LNA and shuts off the LNA bias current.
LNA GAIN
18
NC
No connection. For isolation purposes, this pin is connected to the
ground plane.
19
NC
No connection. For isolation purposes, this pin is connected to the
ground plane.
8-36
Rev A7 010912
Share Link: 