LC72147V Ver la hoja de datos (PDF) - SANYO -> Panasonic
Número de pieza
componentes Descripción
Lista de partido
LC72147V Datasheet PDF : 22 Pages
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Continued from preceding page.
No.
Control block/data
General-purpose counter
control data
CTS, CTE
(6)
GT0, GT1
CTP
CTC
I/O port control data
(7)
IO-1 to I/O-5
Output port data
(8)
OUT1 to OUT5
IFBC port control data
(9)
IFB0, IFB1
LC72147V
Content
• Selects the general-purpose counter input pin (HCTR).
CTS = 1: Selects the HSTR pin.
CTS = 0: Pulls down the HCTR pin.
• General-purpose counter measurement start data
CTE = 1: Starts the counter.
CTE = 0: Resets the counter.
• Determines the measurement time (frequency mode) and number of periods (period
mode).
Related data
Frequency measurement
GT1 GT0
Wait time
Measurement time
CTP = 0 CTP = 1
Period measurement
mode
0
0
4 ms
3 to 4 ms 1 to 2 ms
One period
0
1
8
3 to 4 ms 1 to 2 ms
One period
1
0
32
7 to 8 ms 1 to 2 ms
Two periods
1
1
64
7 to 8 ms 1 to 2 ms
Two periods
• CTP = 0: When the counter has been reset (CTE = 0), pulls down the general-purpose
counter input.
CTP = 1: When the counter has been reset (CTE = 0), does not pull down the general-
purpose counter input, and shortens the wait time.
However, immediately after CTP is set to 1, the counter start must be delayed
until the general-purpose counter input pin has been biased.
• The input sensitivity is reduced when CTC is set to 1. (Sensitivity: 10 to 30 mV rms)
• Data that specifies the I/O direction of the I/O ports.
[Data] = 0: Input port
1: Output port
*: After the power-on reset, the I/O-1, I/O-2, I/O-4, and I/O-5 are set up as input ports. I/O-3
is set up as an output port.
OUT1 to OUT5
ULD
• Data that determines the output from output ports O-1 to O-5.
[Data] = 1: Open or high level.
0: Low
*: Invalid when the corresponding port is set up as an input port or as the unlock state
indicator output.
I/O-1 to I/O-5
ULD
• Determines the 3-value output of the IFBC port.
IFB0 IFB1
0
0
0
1
1
0
1
1
IFBC output
Mid (Vreg/2 = 1.5 V)
Low (0 V)
Mid (Vreg/2 = 1.5 V)
High (Vreg = 3.0 V)
*: When PLL inhibit and crystal oscillator stop mode (R0 = 0, R1 = R2 = R3 = 1), the IFBC
output is set to the open state. This output goes to the mid level after the power-on reset.
Continued on next page.
No. 6675-11/22
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