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AD9432

12-Bit, 80 MSPS/105 MSPS A/D Converter

Analog Devices 

AD9432

EVALUATION BOARD

The AD9432 evaluation board offers an easy way to test the

AD9432. It requires an analog signal, encode clock, and power

supplies as inputs. The clock is buffered on the board to provide

the clocks for an on-board DAC and latches. The digital outputs

and output clock are available at a standard 37-pin connector P7.

Power Connector

Power is supplied to the board via two detachable 4-pin power

strips P30, P40.

P40

P1 VCC2 5 V/165 mA

P2 GND

P3 VCC 5 V/200 mA

P4 GND

DAC Supply

ADC Analog Supply

P30

P5

No Connect

P6

No Connect

P7 VD 3.3 V /105 mA Latch, ADC Digital Output Supply

P8 GND

Analog Inputs

The evaluation board accepts a 2 V p-p analog input signal at

SMB connector P2. This single-ended signal is ac-coupled by

capacitor C11 and drives a wideband RF transformer T1 (Mini-

Circuits ADT1-1WT) that converts the single-ended signal to a

differential signal. (The AD9432 should be driven differentially to

provide optimum performance.) The evaluation board is shipped

with termination resistors R4, R5, which provide the effective

50 Ω termination impedance; input termination resistor R10 is

optional. Note: The second harmonic distortion that some RF

transformers tend to introduce at high frequencies can be reduced

by coupling two transformers in series as shown in Figure 13.

(Improvements on the order of 3 dB–4 dB can be realized.)

C2

0.1␮F T1

IN

T2

R1

25⍀

TO AIN+

R2

25⍀

C1

0.1␮F

TO AIN–

Figure 13. Improving Second Harmonic Distortion

Performance

TEK STOP: 5.00GS/s

14 ACQS

[T]

T

C1 MAX

3.4V

C1 MIN

2.5mV

C1 FREQ

49.995MHz

LOW SIGNAL

AMPLITUDE

2

CH1 500mV CH2 500mV M 5.00ns CH1

CH3 2.00V

3.00V

Figure 14. Analog Input Levels

The full-scale analog inputs to the ADC should be two 1 V p-p

signals 180 degrees out of phase with each other, as shown in

Figure 14. The analog inputs are dc biased by two on-chip

resistor dividers that set the common-mode voltage to approxi-

mately 0.6 × VCC (0.6 × 5 = 3 V). AIN+ and AIN– each vary

between 2.5 V and 3.5 V as shown in the two upper traces in Fig-

ure 14. The lower trace is the input at SMB P2 (on a 2 V/div scale).

Encode

The encode input to the board is at SMB connector P3. The

(>1 V p-p) input is ac-coupled and drives two high-speed differ-

ential line receivers (MC10EL16). These receivers provide

subnanosecond rise times at their outputs—a requirement for

the ADC clock inputs for optimum performance. The EL16

outputs are PECL levels and must be ac-coupled to meet the

common-mode dc levels required at the AD9432 encode inputs.

A PECL/TTL translator (MC100ELT23), provides the clocks

required at the output latches, DAC, and 37-pin connector.

Note: Jitter performance on the clock source is critical at this

performance level; a stable, crystal-controlled signal generator is

used to generate all of the ADC performance plots. Figure 15

shows the Encode+ clock at the ADC. The 3 V latch clock

generated on the card is also shown in the plot.

TEK STOP: 5.00GS/s

86 ACQS

[T]

C1 MAX

2.33V

C1 MIN

810mV

T

C1 FREQ

106.3167MHz

LOW

SIGNAL

AMPLITUDE

2

CH1 1.00V CH2 1.00V M 5.00ns CH1

1.20V

Figure 15. Encode+ Clock and Latch Clock

–12–

REV. E

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