MAS9142(2000) Ver la hoja de datos (PDF) - Micro Analog Systems Oy

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MAS9142
(Rev.:2000)

Power Amplifier Controller (PAC) and 2.8 V, 50 mA LDO Voltage Regulator

Micro Analog Systems Oy 

$33/,&$7,21 ,1)250$7,21

The application circuit diagram is shown in Fig 2.

The following comments apply to the schematic:

1. The VSS1 (ground for PAC) and VSS2 (ground

for regulator) must be connected together.

2. There are no external biasing components

needed for the RF rectifier, they are on the chip.

3. When the external RF decoupling capacitor

&RFD from the directional coupler (not shown) is

used PSENSE pin must be left unconnected.

DA9142.000

26 April, 2000

When the integrated RF decoupling capacitor is

used, the output of directional coupler goes

directly to the PSENSE pin and connection

between directional coupler and DRECT pin is

not connected.

4. Stabilizing capacitor &FB between the OAMINUS

and OAOUT pins is optional.

V BAT

Transmit Enable

&FB *

V SS1

BAT62

GSM power ramping

signal (1:7)

VSS1

Regulator Enable

&BYP 100nF

V SS2

0$6

1 OAM

OAO 16

2 DTEMP VDD1 15

3 DRECT TXEN 14

4 PSENSE VAPC 13

5 VSS1 VROUT 12

6 RAMP

11

7 CBYPASSVDD2 10

8 VRCTRL VSS2 9

&VD1 100nF

V SS1

CVD2 68pF

2.8V 50mA

&VD3

330nF

&REG

1µF

V SS2

&BST

100µF

GSM TX

Input Signal

V BAT

&APC * 100pF

V SS1

V APC

Power

Amplifier

0-2.2V,

max 3 mA

Fig. 2

Directional

Coupler

Ant.

5M 50Ω VSS1

7 (11)

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