HI5735(1998) Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Lista de partido

HI5735
(Rev.:1998)

12-Bit, 80 MSPS, High Speed Video D/A Converter

Intersil 

HI5735

Electrical Specifications TAAVE=E2,5DoVCEfEor=A-l4l .T9y4pitcoa-l5V.a4l6uVe,sVC(CCo=n+ti4n.7u5edto) +5.25V, VREF = Internal

PARAMETER

TEST CONDITIONS

HI5735BI

TA = 0oC TO 70oC

MIN TYP MAX

UNITS

Spurious Free Dynamic Range to Nyquist

(Note 3)

REFERENCE/CONTROL AMPLIFIER

fCLK = 40MHz, fOUT = 2.02MHz, 20MHz Span

fCLK = 80MHz, fOUT = 2.02MHz, 40MHz Span

-

70

-

dBc

-

70

-

dBc

Internal Reference Voltage, VREF

Internal Reference Voltage Drift

(Note 4)

(Note 3)

-1.27

-

-1.23

50

-1.17

-

V

µV/oC

Internal Reference Output Current Sink/Source (Note 3)

Capability

-125

-

+50

µA

Internal Reference Load Regulation

Input Impedance at REF OUT pin

IREF = 0 to IREF = -125µA

(Note 3)

-

50

-

µV

-

1.4

-

kΩ

Amplifier Large Signal Bandwidth (0.6VP-P)

Sine Wave Input, to Slew Rate Limited (Note 3)

-

3

-

MHz

Amplifier Small Signal Bandwidth (0.1VP-P)

Sine Wave Input, to -3dB Loss (Note 3)

-

10

-

MHz

Reference Input Impedance

(Note 3)

-

12

-

kΩ

Reference Input Multiplying Bandwidth (CTL IN)

DIGITAL INPUTS (D9-D0, CLK, INVERT)

RL = 50Ω, 100mV Sine Wave, to -3dB Loss at

IOUT (Note 3)

-

200

-

MHz

Input Logic High Voltage, VIH

Input Logic Low Voltage, VIL

Input Logic Current, IIH

Input Logic Current, IIL

Digital Input Capacitance, CIN

TIMING CHARACTERISTICS

(Note 4)

(Note 4)

(Note 4)

(Note 4)

(Note 3)

2.0

-

-

V

-

-

0.8

V

-

-

400

µA

-

-

700

µA

-

3.0

-

pF

Data Setup Time, tSU

Data Hold Time, tHLD

Propagation Delay Time, tPD

CLK Pulse Width, tPW1, tPW2

POWER SUPPLY CHARACTERISITICS

See Figure 1 (Note 3)

See Figure 1 (Note 3)

See Figure 1 (Note 3)

See Figure 1 (Note 3)

3.0 2.0

-

ns

0.5 0.25

-

ns

-

4.5

-

ns

3.0

-

-

ns

IEEA

IEED

ICCD

Power Dissipation

(Note 4)

(Note 4)

(Note 4)

(Note 4)

-

42

50

mA

-

70

85

mA

-

13

20

mA

-

650

-

mW

Power Supply Rejection Ratio

VCC ±5%, VEE ±5%

-

5

-

µA/V

NOTES:

2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 1.28mA). Ideally

the ratio should be 16.

3. Parameter guaranteed by design or characterization and not production tested.

4. All devices are 100% tested at 25oC. 100% production tested at temperature extremes for military temperature devices, sample tested

for industrial temperature devices.

5. Dynamic Range must be limited to a 1V swing within the compliance range.

1624

Share Link: