HI5735 Ver la hoja de datos (PDF) - Intersil
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HI5735 Datasheet PDF : 11 Pages
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HI5735
Absolute Maximum Ratings
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . . -5.5V
Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DVCC to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA
Voltage from CTRL IN to AVEE . . . . . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range . . . . . . . . . . . . . . . . . .-3.7V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range
HI5735KCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVEE, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal TA = 25oC for All Typical Values
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
SYSTEM PERFORMANCE
Resolution
12
-
-
Bits
Integral Linearity Error, INL
(Note 4) (“Best Fit” Straight Line)
-
0.75 1.5
LSB
Differential Linearity Error, DNL
(Note 4)
-
0.5
1.0
LSB
Offset Error, IOS
Full Scale Gain Error, FSE
Offset Drift Coefficient
(Note 4)
(Notes 2, 4)
(Note 3)
-
20
75
µA
-
1
10
%
-
-
0.05 µA/oC
Full Scale Output Current, IFS
Output Voltage Compliance Range
(Note 3)
-
20.48
-
mA
-1.25
-
0
V
DYNAMIC CHARACTERISTICS
Throughput Rate
(Note 5)
80
-
-
MSPS
Output Voltage Full Scale Step
Settling Time, tSETT Full Scale
Single Glitch Area, GE (Peak)
Doublet Glitch Area, (Net)
To ±0.5 LSB Error Band RL = 50Ω
(Note 3)
RL = 50Ω (Note 3)
-
20
-
ns
-
5
-
pV-s
-
3
-
pV-s
Output Slew Rate
RL = 50Ω, DAC Operating in Latched Mode
(Note 3)
-
1,000
-
V/µs
Output Rise Time
RL = 50Ω, DAC Operating in Latched Mode
(Note 3)
-
675
-
ps
Output Fall Time
RL = 50Ω, DAC Operating in Latched Mode
(Note 3)
-
470
-
ps
Differential Gain
Differential Phase
Spurious Free Dynamic Range to Nyquist
(Note 3)
RL = 50Ω (Note 3)
RL = 50Ω (Note 3)
fCLK = 40MHz, fOUT = 2.02MHz, 20MHz Span
fCLK = 80MHz, fOUT = 2.02MHz, 40MHz Span
-
0.15
-
%
-
0.07
-
Deg
-
70
-
dBc
-
70
-
dBc
3
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