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AD9561JR

Pulse Width Modulator

Analog Devices 

ANALOG DEVICES FAX-ON-DEMAND HOTLINE - Page

AD9561

Pulse Pattern Example

where F is the CLOCK &equency in Hz. The resistor value

Figure 1 at the top ofthe previous page iJIustrates the PWM

OUT of the AD9561 with various DATA and CONTROL

determined by the equation wj]]generate a current near center-

range ofthe autocalibration circuit.

inputs. The DATA format is Binary. In the Pulse Pattern

Example, the Hexadecimal format is used, i.e., FFH represents

decimal 255.

The top line shows the CLOCK; the second shows DATA and

Autocalibration

The AD9561 should be calibrated when power is applied to the

system or after a power reduce cycle.

CONTROL inputs, which are latched on the rising edge of

CLOCK. The third line shows the resulting pulse.

~L~A~

I

\

The AD956l DATA and CONTROL inputs are double

latched. The OUTPUT pulse labeled "Pulse N" results from

~~ 1JJsM.I\N

DATA and CONTROL values latched in by the first CLOCK,

i11ustratingthe one CLOCK period timing delay.

The CONTROL value number for pulse one is shown as xx.

] L=~ { This means the value is not important because a 100% pulse

wj]]be output for any CONTROL value for DATA value 255 or

FFH. Likewise, OUTPUT Pulse N is noted as 100% DNC (do

not care), also noting that CONTROL value is unimportant.

The fourth DATA/CONTROL value is CO/OX.This indicates

Othat the level for LEM/TEM is unimportant when SEM/DEM is

logic Level "0".

B Selecting RSET

Because the AD9561 must provide full range coverage of the

S CLOCK pulse period, the ramp time must be matched to the

O CLOCK period. An components for the ramp generators, except

RsET,are integrated in the AD9561.

L RsET,is selected by the user to set the ramp time close to the

E CLOCK period. The ramps are generated by constant current

sources charging on-chip capacitors.

T RsETcan be chosen in the range from 226 G for 60 MHz

E operation to 16.5 kG for I MHz. Because the absolute value of

~,,~

Figure 4. Autocalibration Timing

Autocalibration is initiated by applying a pulse of 1 /lSminimum

duration to Pin 17, CAL START. The CLOCK pulseshouldbe

appliedcontinuouslyduring calibration. As Figure 4 shows, the

initial state of CAL OUT is not known.

During the CAL IN pulse, all internal logic is initialized for

calibration and proper synchronization once calibration is

complete; the faJJingedge of CAL IN initiates the Auto-CAL

cycle.

Auto-CALis not affected by the code applied to the DATA or

CONTROL inputs. However, to assure that no pulses are

generated during calibration, it is suggested that all digital

inputs be held at Logic "0."

On the faJJingedge of CAL IN, the ramp's slope is set as slow as

possible for the current RsET. Figure 4 shows the RAMP slope

increasing as autocalibration adds sman incremental currents,

the on-chip capacitor can vary by :t20%, the autocalibration

until it crosses the internal REF LO before the end of the

circuit is included to fine tune the matching of the ramp time to

the CLOCK period.

CLOCK period.

100

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Z

!!j 10

C1

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IL

::.::

g

d

1

0

"'-.

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1

RSET- ko

"

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10

20

RAMP

ENDOF CLOCK CYCLE

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- REFLO

--,

TIME

~ -=:t>

Figure 5. Autocalibration Conceptual

Figure 3. RSET Values vs. CLOCK Frequency

Figure 3 shows approximate values for RsET over the operating

frequency range. The following equation should be used to

determine RsET:

R= 30.2068x1O9

F1.04414

The calibration current is incremented on each 32nd CLOCK

pulse until the fuJI-scale ramp time is equal to the period of the

CLOCK. CaJCompleteis detectedand CAL OUT goeshigh

when the ramp crosses REF LO before it is reset by the next

CLOCK. With a maximum of 64 incremental increases, the

maximum autocalibration time, tAG,can be calculated by the

equation:

32x64

where:

tAG =-

Fc

Fc = CLOCK frequency in Hertz

REV. 0

-5-

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