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AD9561JR

Pulse Width Modulator

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AD9561

Grounding and Bypassing

To reiterate the key layout considerations, high speed

Because the AD9561 uses analog circuits to achieve its superb

digital traces should not be located near the RsETpin or

gray scale resolution, caution must be exercised when incorpo-

under the center of the IC body.

rating it into the mostly digital controHer card for a printer.

Achieving the accuracy designed into the AD9561 requires that

interference due to improper grounding, power supply noise and

digital coupling be minimized by foJJowinggood layout practices.

It is strongly urged that all foJJowingrecommendations be

foHowed.

A final interface consideration relates to rise/fan time of

the high speed signals. Some logic families have rise and

fan times as fast as 2 V/ns. This can result in on-chip

parasitic coupling of these signals into the analog section.

The undesirable effect can be eliminated by inserting

series resistors in the DATA, SEMIDEM and LEMI

Factory characterization proves that a single ground plane

TEM connections. These resistors, in conjunction with the

dedicated to the AD9561 is most effective. This is atypical of

capacitance of the input pin and bond pad, wiJ]form a low

many mixed signal circuits that use separate analog and digital

pass filter to limit slew rate of the signals. The value of

grounds. Due to the operating speed of the AD9561, separate

these resistors should be chosen based on trading off slower

grounds result in erratic performance, which is eliminated by

rise and fan time to possible interference to set up and hold

OBSOLETE using a single isolated ground plane. This is because the DATA

"low" value can be different from the ground value of the

AD9561. AH pins on the AD9561 labeled GROUND should

be connected to the single dedicated ground plane. For best

results, it is suggested that this plane be in the first interior layer

under the IC. To assure logic level compatibility from the drive

circuits to the AD9561, a single connection to the board's main

ground is necessary.

The connection between the dedicated ground plane and the

board's main ground should be parallel to the path of the digital

signals interfacing to the AD9561. High frequency return current

seeks the path most paranel to the signal current. Whenever a

parallel path does not exist, ground bounce results.

CLOCK, DATA and CONTROL signal traces should run

from the drive logic to the AD9561 in a group parallel to the

connection between the system ground and the AD9561

ground. Using more than one signal plane wiJ] permit these

times for faster clock rates.

Power supply noise can also disrupt the linear circuits of

the AD9561. Since switching power supplies are becoming

the norm in most systems, caution should be exercised to

minimize switching noise reaching the AD95 6I. The IC is

designed for maximum power supply rejection. However,

frequency content of switching supply noise often exceeds

the frequency range of highest rejection. The preferred

method would be to use a linear regulator from a higher

supply voltage. If this is not practical, insert a ferrite bead

in series with the supply connection. Ifpossible, a VDD

plane or a substantial width trace should connect VDDto

Pin 7 first and then connect to each of the other VDDpins

with wide traces. Thorough decoupling wiJIcomplete a low

pass filter for the supply.

All VDDconnections should be connected together. 0.1 W

chip capacitors should be connected as closely as possible

traces to be as close to the ground interconnection as possible.

to each VDDpin to the deillcated ground plane. Laboratory

This results in lowest impedance ground return and minimum

results indicate that performance is maximized when these

ground interference due to digital switching.

chip capacitors are mounted on the same side of the PC

Attention to subtle layout characteristics can yield significant

improvement in performance of high speed mixed signal ICs.

The AD9561 pinouts were chosen for maximum isolation of

sensitive pins such as RsET' The Pin 1 end of the IC should be

oriented toward the source of the high speed digital inputs.

This wiJ] help assure that these signal runs are short, with

essentiaHy the same length, thus having equal propagation

delays. Most importantly, it wiH facilitate orienting traces to

card as the AD95 61. If mounting chip components on the

same side as the AD9561 is not a preferred manufacturing

method, due consideration is encouraged to make an excep-

rion, at least in the case of RsETand as many decoupling

capacitors as practical. AdditionaHy, a 10 W tantalum

capacitor should decouple the supply on the AD9561 side

of the regulator or ferrite bead, also to the dedicated

ground plane.

minimize coupling.

For a recommended layout, see the AD95611PCB data

High speed digital traces including DATA, CLOCK, SEMI

DEM, LEMiTEM and the OUTPUT should not pass under the

sheet. A copy can be obtained by caHingApplications

Support at 1-800-ANALOGD.

body of the IC. The CLOCK, in particular, should enter

perpendicular to the IC.

For best results, the OUTPUT trace should exit perpendicular

to the IC and pass through a via to a signal layer under the

ground plane. This trace or any resistor or other component

of the output circuit should not be paraJJel to RsETas electro-

magnetic coupling can occur, causing the ramp current reference

to be noisy and linearity to deteriorate.

OptimaHy, RsETshould be a chip resistor located on the same

side of the board as the AD9561. It should be located close to

Pin 14, without being close to the other IC pins. RsETshould

be on the top of the board with the AD9561 with no vias to add

stray reactance and adilltional coupling paths.

REV. 0

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