XR16C864 Ver la hoja de datos (PDF) - Exar Corporation
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XR16C864 Datasheet PDF : 51 Pages
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XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift Data Bit
Register (RSR) Validation
Receive Data Characters
REV. 2.2.0
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X Clock
128 bytes by 11-bit
wide
FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Receive
Data FIFO
Receive
Data
Data Bit
Validation
Receive Data Characters
Exam p le
-:RX FIFO trigger level selected at 16
bytes
Data falls to
8
(See Note Below)
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
FIFO
Trigger=16
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to
24
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RXFIFO1
NOTE: Table-B selected as Trigger Table for Figure 9 (Table 11).
2.14 Auto RTS Hardware Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 10):
• Enable auto RTS flow control using EFR bit-6.
• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
16
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