HS-80C86RH Ver la hoja de datos (PDF) - Intersil
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HS-80C86RH Datasheet PDF : 29 Pages
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Burn-In Circuits
HS-80C86RH 40 LEAD DIP
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
CLK
19
22
20
21
T T ≥ 5.0µs
STATIC
NOTES:
15. VDD = +6.5V ±10%.
16. TA = 125oC Minimum.
17. Part is Static Sensitive.
18. Voltages Must Be Ramped.
19. Package: 40 Lead DIP.
20. Resistors:
10kΩ ±10%
(Pins 17, 18, 21-23, 31, 33)
2.7kΩ ±5% (Pins 2-16, 39)
1.0kΩ ±5% 1/10W Min (Pin 19)
Minimum of 5 CLK Pulses
After Initial Pulses, CLK is Left High
Pulses are 50% Duty Cycle Square Wave
HS-80C86RH
HS-80C86RH 40 LEAD DIP
VDD
VDD
1
40
F15
2
39
F16
F14
3
38
LOAD
F13
4
37
LOAD
F12
5
36
LOAD
F11
6
35
LOAD
F10
7
34
LOAD
F9
8
33
MN/MX
F8
9
32
LOAD
F7
10
31
F6
11
30
F5
12
29
LOAD
F4
13
28
LOAD
F3
14
27
LOAD
F2
15
26
LOAD
F1
16
25
LOAD
NMI
17
24
LOAD
18
23
F0
19
22
READY
20
21
RESET
VDD
2.7kΩ
LOAD
2.7kΩ
DYNAMIC
NOTES:
21. VDD = 6.5V ±5% (Burn-In).
22. VDD = 6.0V ±5% (Life Test).
23. TA = 125oC.
24. Package: 40 Lead DIP.
25. Part is Static Sensitive.
26. Voltage Must Be Ramped.
27. Resistors:
10kΩ (Pins 17, 18, 21, 22, 23, 33)
3.3kΩ (Pins 2-16, 19, 30, 31, 39)
2.7kΩ Loads As Indicated
All Resistors Are At Least 1/8W, ±10%
F0 = 100kHz, F1 = F0/2, F2 = F1/2 . . .
RESET, NMI low after initialization.
READY pulsed low every 320ms
MN/MX changes state every 5.24s
9
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