HS-82C37ARH(1995) Ver la hoja de datos (PDF) - Intersil
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HS-82C37ARH Datasheet PDF : 29 Pages
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HS-82C37ARH
Burn-In Circuits (Continued)
HS-82C37ARH 42 LEAD CERAMIC FLATPACK
VDD
1
42
2
41
F0
3
40
4
39
5
38
6
37
7
36
8
35
9
34
10
33
11
32
F0
12
31
F0
F1
13
30
F5
14
29
15
28
16
27
17
26
F1
18
25
F2
19
24
F3
20
23
F4
21
22
HS-82C37ARH 42 LEAD CERAMIC FLATPACK
1
2
LOAD
3
LOAD
4
OPEN
5
6
7
LOAD
8
LOAD
9
LOAD 10
11
12
13
LOAD 14
LOAD 15
OPEN
16
17
18
19
20
21
42
LOAD
41
LOAD
40
LOAD
39
LOAD
38
37
36
35
34
33
32
31
30
29
28
27
OPEN
26
LOAD
25
LOAD
24
23
22
VDD
F5
F4
F3
F2
F1
F0
STATIC CONFIGURATION
NOTES:
1. VDD = +6.0V ± 5%
Part is Static Sensitive
2. TA = +125oC Minimum
Voltage Must be Ramped
3. Resistors:
R1 = 10kΩ ± 10% (Pins 6, 7, 11-13, 16-19)
R2 = 2.7kΩ ± 5% (Pins 1, 2, 21-23, 26-30, 32-36)
F0
VDD
2.7KΩ
LOAD
2.7KΩ
F1
START-UP TIMING
NOTES:
1. F0 is 50% duty cycle square wave pulse burst.
2. 1.0kHz ≤ F0 ≤ 100kHz
F0 is left High after pulse burst
3. 10 cycles ≤ F0 Pulse Burst ≤ 1.0s
4. F1 = Single pulse with width equal to 2 cycles of F0
5. F1 is left Low after pulse burst
6. F1 pulse occurs after start of F0 and ends before F0.
Input levels: 0.9VDD ≤ VIH ≤ VDD, -0.3V ≤ VIL ≤ 0.7V
DYNAMIC CONFIGURATION
NOTES:
1. VDD = 6.5V ± 5% (Burn-In)
2. VDD = 6.0V ± 5% (Life Test)
3. TA = +125oC Minimum
4. Part is Static Sensitive, Voltage Must be Ramped
5. Resistors:
R1 = 10kΩ ± 10% (Pins 6, 7, 11-13, 16-19)
R2 = 2.7kΩ ± 10% (Pins 1, 2, 21-23, 26-30, 32-36, and LOADS)
Spec Number 518058
934
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