5962R9582101VQC Ver la hoja de datos (PDF) - Intersil
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5962R9582101VQC Datasheet PDF : 21 Pages
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Irradiation Circuit
HS-82C37ARH
TOGGLE
CLOCK
RESET
TOGGLE
R
1
R
2
LOAD
3
LOAD
4
NC
5
R
6
R
7
LOAD
8
LOAD
9
LOAD 10
R
11
R
12
R
13
LOAD 2
14
LOAD 2 15
R
16
R
17
R
18
R
19
VSS
20
40 LOAD
39 LOAD
38 LOAD
37 LOAD
R
36
R
35
R
34
R
33
R
32
31
VCC
LOAD
VCC
OUT
2.7kΩ
2.7kΩ
VSS
5.5V
30 LOAD 2
29 LOAD 2
28 LOAD 2
27 LOAD 2
26 LOAD 2
LOAD 2
OUT
2.7kΩ
25 LOAD 2
VSS
24 LOAD 2
23 LOAD 2
22 LOAD 2
21 LOAD 2
NOTES:
29. R = 47kΩ
30. Pins with Load: 3, 4, 8, 9, 10, 37-40
Pins with Load2: 14, 15, 21-30
Pins Brought Out: 12 (Clock), 13 (Reset)
31. VDD = 5.5V ±0.5V
Functional Description
The HS-82C37ARH Direct Memory Access Controller is
designed to improve the data transfer rate in systems which
must transfer data from an I/O device to memory, or move a
block of memory to an I/O device. It will also perform
memory-to-memory block moves, or fill a block of memory
with data from a single location. Operating modes are
provided to handle single byte transfers as well as
discontinuous data streams, which allows the
HS-82C37ARH to control data movement with software
transparency.
The DMA controller is a state-driven address and control
signal generator, which permits data to be transferred
directly from an I/O device to memory or vice versa without
ever being stored in a temporary register. This can greatly
increase the data transfer rate for sequential operations,
compared with processor moves or repeated string
instructions. Memory-to-Memory operations require
temporary internal storage of the data byte between
11
generation of the source and destination addresses, so
Memory-to-Memory transfers take place at less than half the
rate of I/O operations, but still much faster than with central
processor techniques. The maximum data transfer rate
obtainable with the HS-82C37ARH is approximately
2.5 Mbytes/second, for an I/O operation using the compressed
timing option and 5MHz clock.
The block diagram of the HS-82C37ARH is shown on page
2. The Timing and Control Block, Priority Block, and internal
registers are the main components. Figure 8 lists the name
and size of the internal registers. The Timing and Control
Block derives internal timing from the CLOCK input, and
generates external control signals. The Priority Encoder
Block resolves priority contention between DMA channels
requesting service simultaneously.
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