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5962R9582001QJC

Radiation Hardened CMOS Static Clock Controller/Generator

Intersil 

Functional Diagram

RES (17)

START (11)

CSYNC (1)

SLO/FST (12)

F/C (19)

EFI (20)

X2 (22)

X1 (23)

S2/STOP (15)

S1 (14)

SO (13)

RDY1 (4)

AEN1 (3)

AEN2 (7)

RDY2 (6)

ASYNC (21)

HS-82C85RH

RESTART

LOGIC

RESTART

RESET PULSE

CONDITIONING

LOGIC

EXTERNAL

FREQUENCY

SELECT

OSC

OSCILLATOR

SYNC

LOGIC

SYNC

SP÷E2E5D6 OSERL÷E1CT

MASTER

OSC

CLOCK

L(O÷G3I)C

SELECTED OSC

PERIPHERAL

CL(÷O6C)K

STOP

LOGIC

HALT

READY

SELECT

READY

SYNC

(24) VDD

(9) GND

AC Test Circuit

FROM OUTPUT

UNDER TEST

NOTES:

1. R = 370Ω at V = 2.25 for CLK and CLK50 outputs.

2. R = 494Ω at V = 2.87 for all other outputs.

3. CL = 50pF.

4. CL Includes probe and jig capacitance.

VDD

R (NOTES 1, 2)

CL (NOTE 4)

(16) RESET

(8) CLK

(10) CLK50

(2) PCLK

(18) OSC

(5) READY

4

FN3044.3

April 20, 2007

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