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M37641F8

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

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MITSUBISHI MICROCOMPUTERS

7641 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer Y

Timer Y is a 16-bit timer that can be selected in one of four modes.

(1) Timer Mode

The timer counts one of the internal clock φ divided by 8, 16, 32,

64.

q TYOUT Output Function

In the timer mode, a signal of which polarity is inverted each time

the timer underflows is output from the CNTR1 pin. This is enabled

by setting the Timer Y Output Control Bit to “1”.

When the CNTR1 Active Edge Switch Bit is “0”, the CNTR1 pin

starts pulses output beginning at “H”; when this bit is “1”, the

CNTR1 pin starts pulses output beginning at “L”.

When using a timer in this mode, set the port P44 direction regis-

ter to output mode.

(2) Period Measurement Mode

CNTR1 interrupt request is generated at a rising/falling edge of

CNTR1 pin input signal. Simultaneously, the value in timer Y latch

is reloaded in timer Y and timer Y continues counting down. Ex-

cept for the aforementioned operation, the operation in period

measurement mode is the same as in timer mode. (The TYOUT

output function is not usable.)

The timer value just before the reloading at rising/falling of CNTR1

pin input signal is retained until the timer Y is read once after the

reload.

The rising/falling timing of CNTR1 pin input signal is found by

CNTR1 interrupt.

When the CNTR1 Active Edge Switch Bit is “0”, the falling edge is

detected; when this bit is “1”, the rising edge is detected.

When using a timer in this mode, set the port P44 direction regis-

ter to input mode.

(3) Event Counter Mode

The timer counts signals input through the CNTR1 pin.

Except for this, the operation in event counter mode is the same

as in timer mode. (The TYOUT output function is not usable.)

When the CNTR1 Active Edge Switch Bit is “0”, the rising edge is

counted; when this bit is “1”, the falling edge is counted.

When using a timer in this mode, set the port P44 direction regis-

ter to input mode.

(4) Pulse Width HL Continuously Measurement

Mode

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal. Except for this, the operation in

pulse width HL continuously measurement mode is the same as in

period measurement mode.

When using a timer in this mode, set the port P44 direction regis-

ter to input mode.

s Notes

q Timer Y Write Control

If the Timer Y Write Control Bit is “1”, when the value is written in

the address of timer Y, the value is loaded only in the latch. The

value in the latch is loaded in timer Y after timer Y underflows.

If the Timer Y Write Control Bit is “0”, when the value is written in

the address of timer Y, the value is loaded in the timer Y and the

latch at the same time.

When the value is to be written in latch only, unexpected value

may be set in the high-order timer if the writing in high-order latch

and the underflow of timer Y are performed at the same timing.

q CNTR1 Interrupt Active Edge Selection

The CNTR1 interrupt active edge depends on the selection of

CNTR1 Active Edge Switch Bit.

However, in pulse width HL continuously measurement mode,

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal regardless of the setting of

CNTR1 Active Edge Switch Bit.

b7

b0

Timer Y mode register (address 002816)

TYM

Timer Y write control bit

0: Write value in latch and counter

1: Write value in latch only

Timer Y output control bit

0: TYOUT output disabled

1: TYOUT output enabled

Timer Y count source select bits

b3b2

0 0: φ / 8

0 1: φ / 16

1 0: φ / 32

1 1: φ / 64

Timer Y operating mode bits

b5b4

0 0: Timer mode

0 1: Period measurement mode

1 0: Event counter mode

1 1: Pulse width HL continuously measure-

ment mode

CNTR1 active edge switch bit

0: Count at rising edge in event counter mode

Measure the falling edge to falling edge

period in period measurement mode

Falling edge active for interrupt

Start from “H” output for TYOUT signal

1: Count at falling edge in event counter mode

Measure the rising edge to rising edge

period in period measurement mode

Rising edge active for interrupt

Start from “L” output for TYOUT signal

Timer Y count stop bit

0: Count start

1: Count stop

Fig. 21 Structure of timer Y mode register

26

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