M37641F8 Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
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M37641F8 Datasheet PDF : 149 Pages
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MITSUBISHI MICROCOMPUTERS
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
UARTx mode register (addresses 003016, 003816)
UxMOD
UART clock select bit (CLK)
0: φ
1: SCSGCLK
UART clock prescaling select bits (PS)
b2b1
0 0: UART clock divided by 1
0 1: UART clock divided by 8
1 0: UART clock divided by 32
1 1: UART clock divided by 256
Stop bit length select bit (STB)
0: 1 stop bit
1: 2 stop bits
Parity select bit (PMD)
0: Even parity
1: Odd parity
Parity enable bit (PEN)
0: Parity checking disabled
1: Parity checking enabled
UART character length select bit
b7b6
0 0: 7 bits
0 1: 8 bits
1 0: 9 bits
1 1: Not available
b7
b0
b7
UARTx status register (addresses 003216, 003A16)
UxSTS
Transmit complete flag (TCM)
0: Transmit shift in progress
1: Transmit shift completed
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Parity error flag (PER)
0: No error
1: Parity error
Framing error flag (FER)
0: No error
1: Framing error
Overrun error flag (OER)
0: No error
1: Overrun error
Summing error flag (SER)
0: (FER) U (OER) U (SER) = 0
1: (FER) U (OER) U (SER) = 1
Reserved bits (“0” at read/write)
Fig. 30 Structure of UART related registers
b0
UARTx control register (addresses 003316, 003B16)
UxCON
Transmit enable bit (TEN)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (REN)
0: Receive disabled
1: Receive enabled
Transmit initialization bit (TIN)
0: No action.
1: Initializing
Receive initialization bit (RIN)
0: No action.
1: Initializing
Transmit interrupt source select bit (TIS)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
CTS function enable bit (CTS_SEL)
0: CTS function disabled
1: CTS function enabled
RTS function enable bit (RTS_SEL)
0: RTS function disabled
1: RTS function enabled
UART address mode enable bit (AME)
0: Address mode disabled
1: Address mode enabled
b0
0 0 0 0 UARTx RTS control register (addresses 003616, 003E16)
UxRTSC
Reserved bits (“0” at read/write)
RTS assertion delay count select bits
b7 b6 b5 b4
0 0 0 0 : No delay; Assertion immediately
0 0 0 1 : 8-bit term assertion at “H”
0 0 1 0 : 16-bit term assertion at “H”
0 0 1 1 : 24-bit term assertion at “H”
0 1 0 0 : 32-bit term assertion at “H”
0 1 0 1 : 40-bit term assertion at “H”
0 1 1 0 : 48-bit term assertion at “H”
0 1 1 1 : 56-bit term assertion at “H”
1 0 0 0 : 64-bit term assertion at “H”
1 0 0 1 : 72-bit term assertion at “H”
1 0 1 0 : 80-bit term assertion at “H”
1 0 1 1 : 88-bit term assertion at “H”
1 1 0 0 : 96-bit term assertion at “H”
1 1 0 1 : 104-bit term assertion at “H”
1 1 1 0 : 112-bit term assertion at “H”
1 1 1 1 : 120-bit term assertion at “H”
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