M616Z08-20MH3TR Ver la hoja de datos (PDF) - STMicroelectronics
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M616Z08-20MH3TR Datasheet PDF : 14 Pages
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M616Z08
Table 5. DC Characteristics
Sym
Parameter
Test Condition(1)
Min
Typ
Max Unit
ILI Input Leakage Current
0V ≤ VIN ≤ VCC
TO Pin(2)
All other inputs
65
125
µA
±1
µA
ILO Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
µA
ICC1(3) Supply Current
VCC = 3.6V
75
mA
ICC3(4)
Supply Current (Standby)
CMOS
VCC = 3.6V,
CE ≥ VCC – 0.2V, f = 0
1
mA
VIL Input Low Voltage
–0.3
0.3VCC
V
VIH Input High Voltage
0.7VCC
VCC + 0.3 V
VOL Output Low Voltage
IOL = 1mA
0.2
V
2.34 to 3.0V VCC–0.2V
VOH Output High Voltage
IOH = –1mA
3.0 to 3.6V VCC–0.3V
V
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 125°C; VCC = 3.0 to 3.6V or 2.34 to 3.0V (except where noted).
2. Input leakage on TO Pin due to internal pull-down to VSS.
3. Average AC current, Outputs open, cycling at tAVAV minimum.
4. All other Inputs at VIL ≤ 0.2V or VIH ≥ VCC –0.2V.
OPERATION
READ Mode
The M616Z08 is in the READ Mode whenever
WRITE Enable (WE0 or WE1) is High with Output
Enable (OE) Low, and Chip Enable (CE) is assert-
ed. This provides access to data from sixteen of
the 131,072 locations in the static memory array,
specified by the 13 address inputs. Valid data will
be available at the sixteen output pins within tAVQV
after the last stable address, providing OE is Low
and CE is Low. If Chip Enable or Output Enable
access times are not met, data access will be
measured from the limiting parameter (tELQV or
tGLQV) rather than the address. Data out may be
indeterminate at tELQX and tGLQX, but data lines
will always be valid at tAVQV.
Figure 5. Address Controlled, READ Mode AC Waveforms
A0-A12
tAVAV
VALID
tAVQV
tAXQX
DQ0-DQ15
Note: CE = Low, OE = Low, WE(0,1) = High.
DATA VALID
AI04210
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