PDM31548SA12ITR Ver la hoja de datos (PDF) - Paradigm Technology

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PDM31548SA12ITR

128K x 16 CMOS 3.3V Static RAM

Paradigm Technology 

PRELIMINARY

Write Cycle 3 Timing Diagram(5) (UB, LB Controlled)

tWC

ADDRESSES

tAS

tAW

tWP

tAH

WE

tCW

CE

tBW

UB, LB

DOUT

DIN

tLZCE(6)

tLZBE(6)

tHZWE(6)

High Impedance

tDS

tDH

Data Stable

PDM31548

AC Electrical Characteristics

Description

-10

-12

-15

-20

WRITE Cycle

WRITE cycle time

Chip enable to end of write

Address valid to end of write

Byte pulse width

Address setup time

Address hold from end of write

Write pulse width

Data setup time

Data hold time

Byte disable to output in low Z(4, 5)

Byte enable to output in high Z(4, 5)

Output disable to output in low Z(4, 5)

Output enable to output in high Z(4, 5)

Write disable to output in low Z(4, 5)

Write enable to output in high Z(4, 5)

Sym Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC 10 — 12 — 15 — 20 — ns

tCW

9 — 10 — 11 — 12 — ns

tAW

9 — 10 — 11 — 12 — ns

tBW

9 — 10 — 12 — 13 — ns

tAS

0 — 0 — 0 — 0 — ns

tAH

0 — 0 — 0 — 0 — ns

tWP

7 — 8 — 9 — 10 — ns

tDS

6 — 7 — 8 — 9 — ns

tDH

0 — 0 — 0 — 0 — ns

tLZBE 1 — 1 — 1 — 1 — ns

tHZBE — 7 — 7 — 8 — 9 ns

tLZOE 0 — 0 — 0 — 0 — ns

tHZOE — 7 — 7 — 8 — 9 ns

tLZWE 1 — 1 — 1 — 1 — ns

tHZWE — 7 — 7 — 8 — 9 ns

8

Rev. 1.3 - 4/13/98

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