AT43312
Pin Description
Pin Description Pin Type Description
OSC1
I
Oscillator Input. Input to the inverting 6 MHz oscillator amplifier.
OSC2
O
Oscillator Output. Output of the inverting oscillator amplifier.
LFT
I
PLL Filter. For proper operation of the PLL, this pin should be connected through a 2.2 nF capacitor in
parallel with a 100 Ω resistor in series with a 10 nF capacitor to ground (GND)
BUS/SELF
I
Hub Power Mode. Input signal that sets the bus or self-powered mode operation. A high on this pin
enables the bus-powered mode, a low the self-powered mode.
VREF
I
Reference Voltage. This is an input pin that should be connected to an external voltage source. VREF
is used internally as the reference voltage by the overload protection circuit to decide whether there is
a problem with a port’s power.
DP0
B
Upstream Plus USB I/O. This pin should be connected to VCC through an external 1.5 KΩ pullup
resistor. DP0 and DM0 form the differential signal pin pairs connected to the Host Controller or an
upstream Hub.
DM0
B
Upstream Minus USB I/O
DP[1:4]
B
Port Plus USB I/O. This pin should be connected to VSS through an external 15 KΩ resistor. DP[1:4]
and DM[1:4] are the differential signal pin pairs to connect downstream USB devices.
DM[1:4]
OVC[1:4]
B
Port Minus USB I/O. This pin should be connected to VSS through an external 15 KΩ resistor.
I
Overcurrent. This is the input signal used to indicate to the AT43312 that an overcurrent is detected at
the port. If OVC is asserted, AT43312 will assert the PWRx pin and report the status to the USB Host.
PWR[1:4]
OD
Power Switch. This is an output signal used to enable or disable the external voltage regulator
supplying power to a port. PWRx is de-asserted when a power supply problem is detected at OVCx.
STAT[1:4]
O
Connect Status. This is an output pin indicating that a port is properly connected. STATx is asserted
when the port is enabled.
VCC3
VCC5
VCCA
GND
Note:
V
3.3V Power Supply
V
5V Power Supply
V
5V Analog Power Supply
V
Ground
Signals with a # are active low.
3