EBS12UC6APS-75L Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EBS12UC6APS-75L

128MB SDRAM S.O.DIMM

Elpida Memory, Inc 

EBS12UC6APS

Pin Capacitance (TA = +25°C, VDD = 3.3V ± 0.3V)

Parameter

Input capacitance

Data input/output capacitance

Symbol

CI1

CI2

CI3

CI4

CI5

CI6

CI/O1

Pins

Address

/RAS, /CAS, /WE

CKE

/CS

CLK

DQMB

DQ

max.

TBD

TBD

TBD

TBD

TBD

TBD

TBD

Unit

Notes

pF

1, 2, 4

pF

1, 2, 4

pF

1, 2, 4

pF

1, 2, 4

pF

1, 2, 4

pF

1, 2, 4

pF

1, 2, 3, 4

AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V) (SDRAM device specification)

-7A/7AL

-75/75L

-80/80L

Parameter

Symbol min. max. min. max. min. max. Unit

System clock cycle time

(CL = 2)

(CL = 3)

tCK 7.5

—

10

—

10

—

ns

tCK 7.5

—

7.5

—

10

—

ns

CLK high pulse width

tCH 2.5

—

2.5

—

3

—

ns

CLK low pulse width

tCL 2.5

—

2.5

—

3

—

ns

Access time from CLK

tAC —

5.4

—

5.4

—

6

ns

Data-out hold time

tOH 2.7

—

2.7

—

2.7

—

ns

CLK to Data-out low impedance

tLZ 1

—

1

—

1

—

ns

CLK to Data-out high impedance

tHZ —

5.4

—

5.4

—

6

ns

Input setup time

tSI

1.5

—

1.5

—

2

—

ns

Input hold time

tHI

0.8

—

0.8

—

1

—

ns

Ref/Active to Ref/Active command period tRC 60

—

67.5 —

70

—

ns

Active to Precharge command period

Active command to column command

(same bank)

Precharge to active command period

Write recovery or data-in to precharge

lead time

Last data into active latency

tRAS

tRCD

tRP

tDPL

tDAL

Active (a) to Active (b) command period tRRD

45

120000 45

120000 48

120000 ns

15

—

20

—

20

—

ns

15

—

20

—

20

—

ns

15

—

15

—

20

—

ns

2CLK +

15ns

—

2CLK +

20ns

—

2CLK +

20ns

—

15

—

15

—

20

—

ns

Transition time (rise and fall)

tT

0.5

5

0.5

5

0.5

5

ns

Refresh period

(8192 refresh cycles)

tREF —

64

—

64

—

64

ms

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.

2. Access time is measured at 1.4V. Load condition is CL = 50pF.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

Notes

1

1

1

1, 2

1, 2

1, 2, 3

1, 4

1

1

1

1

1

1

1

1

Data Sheet E0224E20 (Ver. 2.0)

9

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