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TC520A

SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY

TelCom Semiconductor Inc => Microchip 

SERIAL INTERFACE ADAPTER FOR

TC500 A/D CONVERTER FAMILY

1

TC520A

a range of AZ = INT = 256 counts to 65536 counts). (See

Figure 2). The LOAD VALUE sets the number of counts for

both the AZ and INT phases and directly affects resolution

and speed of conversion. The greater the number of counts

allowed for AZ and INT; the greater the A/D resolution, but

the slower the conversion speed.

The time period required for the DINT phase is a function

of the amount of voltage stored on the integrator during the

INT phase, and the value of VREF. The DINT phase is initiated

by the TC520A immediately after the INT phase, and termi-

nated when the TC5xx A/D converter changes the state of

the CMPTR input of the TC520A (indicating a zero crossing).

In general, the maximum number of counts chosen for DINT

is twice that of INT (with VREF chosen at VIN (max)/2).

Choosing these values guarantees a full count (maximum

resolution) during DINT when VIN = VIN(max).

The IZ phase is initiated immediately following the DINT

phase maintained until the CMPTR input transitions high.

This indicates the integrator is initialized and ready for

another conversion cycle. This phase typically takes 2msec.

Serial Port Control Signals

Communication to and from the TC520A is accom-

plished over a 3 wire serial port. Data is clocked into DIN on

the rising edge of DCLK and clocked out of DOUT on the falling

edge of DCLK. READ must be low to read from the serial port

and can be taken high at any time, which terminates the read

cycle, and releases DOUT to a high impedance state. Con-

version data is shifted to the processor from DOUT in the

following order: Overrange bit (which can also be used as

the 17th data bit), Polarity bit, conversion data (MSB first).

APPLICATIONS

TC500 Series A/D Converter Component Selection

The TC500/500A/510/514 data sheet details the equa-

tions necessary to calculate values for integration resistor

(RINT) and capacitor (CINT); auto zero and reference capaci-

tors CREF and CAZ and voltage reference VREF. All equations

apply when using the TC520A, except integration time (TINT)

and Autozero time (TAZ) are functions of the SYSCLK period

(timebase frequency and LOAD VALUE). TelCom offers a

ready-to-use TC5xx A/D converter design tool on a 3 1/2

inch diskette (Windows format). The TC500 Design Spread-

sheet is an Excel-based spreadsheet that calculates values

for all components as well as the TC520A LOAD VALUE. It

also calculates overall converter performance such as noise

rejection, converter speed, etc. This software is included in

the TC500EV hardware evaluation kit and is also available

free of charge from your local TelCom representative.

TELCOM SEMICONDUCTOR, INC.

TC520A Initialization

Initialization of the TC520A consists of:

2

(1) Power-On RESET of the TC500/520A (forcing the

TC520A into an AZ phase).

(2) Initializing the TC520A LOAD VALUE.

Power-On RESET

3 The TC520A powers-up with A, B = 00 (IZ Phase),

awaiting a high logic state on CMPTR, which must be

initiated by forcing the TC520A into the AZ phase. This can

be accomplished in one of two ways:

(1) External hardware (processor or logic) can momen-

tarily taking LOAD or CE low for a minimum of 100

msec (tAZI); or

4 (2) A .01µF RESET capacitor can be connected from

CE to VCC to generate a power-on pulse on CE.

Load Value Initialization

The LOAD VALUE is the preset value (high byte of the

SYSCLK timing counter) which determines the number of

counts allocated to the AZ and INT phases of conversion.

This value can be calculated using the TC520A spreadsheet

5 within the TC500 Design Spreadsheet software, or can be

setup as shown in the following example:

(1) Select VREF, TDINT

Choose the TC5xx A/D converter reference voltage

(VREF) to be half of the maximum A/D converter

input voltage. For example, if VIN max = 2.5V;

6 choose VREF = 1.75V. This forces the maximum de-

integration time (TDINT) to be equal to twice the

maximum integration time (TINT) ensuring a full

count (maximum resolution) during DINT.

(2) Calculate TINT

The TC520A counter length is 16 bits (65536).

Allowing the full 65536 counts for TDINT results in a

maximum TINT = 65536/2 or 32768.

(3) Select SYSCLK Frequency

7

SYSCLK frequency directly affects conversion time.

The faster the SYSCLK, the faster the conversion

time. The upper limit SYSCLK frequency is deter-

mined by the worst case delay of the TC500 com-

parator (which for the TC500 and TC500A is

3.2µsec). While a faster value for SYSCLK can be

8 used, operation is optimized (error minimized) by

choosing a SYSCLK period (1/SYSCLK frequency)

that is greater than 3.2µsec. Choosing TSYSCLK =

3-43

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