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V54C3128404V

128Mbit SDRAM 3.3 VOLT, BGA PACKAGE 8M X 16 16M X 8 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

6.2 Write Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND NOP

WRITE A

READ B

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, I/O’s

CAS latency = 3

tCK3, I/O’s

DIN A0

don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

DIN A0

don’t care don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

Input data must be removed from the I/O’s at least one clock

cycle before the Read dataAPpears on the outputs to avoid

data contention.

7. Burst Write with Auto-Precharge

Burst Length = 2, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND

BANK A

ACTIVE

NOP

CAS latency = 2

I/O’s

CAS latency = 3

I/O’s

NOP

WRITE A

Auto-Precharge

DIN A0

DIN A0

NOP

DIN A1

DIN A1

NOP

tWR

*

tWR

NOP

NOP

tRP

NOP

tRP

* Begin Autoprecharge

Bank can be reactivated after trp

V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001

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