V53C3128804V Ver la hoja de datos (PDF) - Mosel Vitelic Corporation
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V53C3128804V Datasheet PDF : 45 Pages
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MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Operation
Row Activate
Read
Read w/Autoprecharge
Write
Write with Autoprecharge
Row Precharge
Precharge All
Mode Register Set
No Operation
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Power Down Entry
Power Down Exit
Data Write/Output Enable
Data Write/Output Disable
Device CKE CKE
A0-9,
BS0
State n-1 n CS RAS CAS WE DQM A11 A10 BS1
Idle3
H
X
L
L
H
H
X
V
V
V
Active3
H
X
L
H
L
H
X
V
L
V
Active3
H
X
L
H
L
H
X
V
H
V
Active3
H
X
L
H
L
L
X
V
L
V
Active3
H
X
L
H
L
L
X
V
H
V
Any
H
X
L
L
H
L
X
X
L
V
Any
H
X
L
L
H
L
X
X
H
X
Idle
H
X
L
L
L
L
X
V
V
V
Any
H
X
L
H
H
H
X
X
X
X
Any
H
X
H
X
X
X
X
X
X
X
Idle
H
H
L
L
L
H
X
X
X
X
Idle
H
L
L
L
L
H
X
X
X
X
Idle
H
X
X
X
(Self Refr.) L
H
X
X
X
X
L
H
H
X
Idle
H
X
X
X
Active4
H
L
X
X
X
X
L
H
H
X
Any
H
X
X
X
(Power
L
H
X
X
X
X
Down)
L
H
H
L
Active
H
X
X
X
X
X
L
X
X
X
Active
H
X
X
X
X
X
H
X
X
X
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Power Down Mode can not entry in the burst cycle.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
7
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