A63L73321 Ver la hoja de datos (PDF) - AMIC Technology

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A63L73321

128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output

AMIC Technology 

Timing Waveforms (continued)

CLK

ADSP

tKC

tKH

tKL

tADSS

tADSH

ADSC

ADDRESS A1

GW,BWE,

BW1-BW4

(NOTE 3)

CE

(NOTE 2)

tAS tAH

A2

tCES

tCEH

ADV

A3

A4

tWS tWH

A63L73321 Series

A5

A6

OE

DIN

DOUT

tKQ

High-Z

tOEHZ

Q(A1)

Q(A2)

Back-to-Back READs

tDS

tDH

D(A3)

Single WRITE

tOELZ

tKQ

Q(A4)

(NOTE 1)

Q(A4+1)

Q(A4+2)

BURST READ

Q(A4+3)

D(A5)

D(A6)

Back-to-Back

WRITEs

Don't Care

Undefined

Read/Write Timing

Notes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following

A4.

2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE is LOW and CE2 is HIGH,

When CE is HIGH, CE2 is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC , or ADV cycle is

performed.

4. Byte Write enables are decided by means of a Write truth table.

5. Back-to-back READs may be controlled by either ADSP or ADSC

PRELIMINARY (June, 1999, Version 0.1)

13

AMIC Technology, Inc.

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