MT9044 Ver la hoja de datos (PDF) - Mitel Networks
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MT9044 Datasheet PDF : 30 Pages
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Advance Information
MT9044
Pin Description (continued)
Pin # Pin #
PLCC MQFP
Name
Description
12
6
RSP
Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing
pulse, which marks the end of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
13
7
F0o Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is typically
used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 20.
14
8
TSP Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
15
9
F8o Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse,
which marks the beginning of a frame. See Figure 20.
16
10
C1.5o Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
17
11
18
12
AVdd
C3o
Analog Vdd. +5VDC nominal.
Clock 3.088MHz (CMOS Output). This output is used in T1 applications.
19
13
C2o Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at
2.048Mb/s.
20
14
C4o Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at
2.048Mb/s and 4.096Mb/s.
21
15
C19o Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.
22
16
ACKi
Analog PLL Clock Input (CMOS Input). This input clock is a reference for an
internal analog PLL. This pin is internally pulled down to VSS.
24
18
ACKo Analog PLL Clock Output (CMOS Output). This output clock is generated by
the internal analog PLL.
25
19
C8o Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at
8.192Mb/s.
26
20
C16o
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with
a 16.384MHz clock.
27
21
C6o Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
29
23 HOLDOVER Holdover (CMOS Output). This output goes to a logic high whenever the digital
PLL goes into holdover mode.
30
24
GTi Guard Time (Schmitt Input). This input is used by the MT9044 state machine in
both Manual and Automatic modes. The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode, and Primary
Holdover Mode and Secondary Normal Mode. The logic level at this input is gated
in by the rising edge of F8o. See Tables 4 and 5.
32
26
GTo Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o,
buffered and output on GTo. This pin is typically used to drive the GTi input through
an RC circuit.
33
27
LOS2
Secondary Reference Loss (TTL Input). This input is normally connected to the
loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the
SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs
control the MT9044 state machine when operating in Automatic Control. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled
down to VSS.
3
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