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LTC1555C

SIM Power Supply and Level Translator

Linear Technology 

LTC1555/LTC1556

APPLICATIONS INFORMATION

reduce the ripple. A larger COUT capacitor (22µF or greater)

will reduce both the low and high frequency ripple due to

the lower COUT charging and discharging dV/dt and the

lower ESR typically found with higher value (larger case

size) capacitors. A low ESR ceramic output capacitor will

minimize the high frequency ripple, but will not reduce the

low frequency ripple unless a high capacitance value is

chosen (10µF or greater). A reasonable compromise is to

use a 10µF to 22µF tantalum capacitor in parallel with a 1µF

to 3.3µF ceramic capacitor on VOUT to reduce both the low

and high frequency ripple. An RC filter may also be used

to reduce high frequency voltage spikes (see Figure 1).

VCC

LTC1555/

LTC1556

VCC

+ 15µF

TANTALUM

2Ω

10µF

SIM

1µF VCC

CERAMIC

SIM

VCC

10µF

LT1555/56 F01

Figure 1. VCC Output Ripple Reduction Techniques

Shutting Down the DVCC Supply

To conserve power, the DVCC supply may be shut down

while the VIN supply is still active. When the DVCC supply

is brought to 0V, weak internal currents will force the

LTC1555/LTC1556 into shutdown mode regardless of the

voltages present on the M0 and M1 pins. However, if the

M0 and M1 pins are floating or left connected to DVCC as

the supply is shut down, the parts may take several

DVCC

M0

0V

DVCC

M1

0V

DVCC

DVCC

0V

VCC

VCC

0V

1555/56 F02

Figure 2. Recommended DVCC Shutdown and Start-Up Timing

hundred milliseconds to completely shut down. To ensure

prompt and proper VCC shutdown, always force the M0

and M1 pins to a logic low state before shutting down the

DVCC supply (see Figure 2). Similarly, bring the DVCC

supply to a valid level before allowing the M0 and M1 pins

to go high when coming out of shutdown. This can be

achieved with pull-down resistors from M0 and M1 to

GND if necessary. (Note: shutting down the DVCC supply

with VIN active is not recommended with early date code

material. Consult factory for valid date code starting point

for shutting down the DVCC supply.)

Level Translators

All SIMs and smart cards contain a clock input, reset input

and a bidirectional data input/output. The LTC1555/

LTC1556 provide level translators to allow controllers to

communicate with the SIM (see Figures 3a and 3b). The

CLK and RST inputs to the SIM are level shifted from the

controller supply rails (DVCC and GND) to the SIM supply

rails (VCC and GND). The data input to the SIM may be

provided two different ways. The first method is to use the

DATA pin as a bidirectional level translator. This configu-

ration is only allowed if the controller data output pin is

open drain (all SIM I/O pins are open drain). Internal pull-

up resistors are provided for both the DATA pin and the

CLK TO SIM

RST TO SIM

DATA TO/FROM SIM

CONTROLLER

SIDE

LTC1555/LTC1556

CIN

CLK

RIN

RST

DATA

I/O

DDRV VCC

DVCC

SIM SIDE

1555/56 F3a

Figure 3a. Level Translator Connections for

Bidirectional Controller DATA Pin

LTC1555/LTC1556

CLK TO SIM

RST TO SIM

DATA FROM SIM

DATA TO SIM

CONTROLLER

SIDE

CIN

CLK

RIN

RST

DATA

I/O

DDRV VCC

DVCC

SIM SIDE

1555/56 F3b

Figure 3b. Level Translator Connections for

One-Directional Controller Side DATA Flow

8

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