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MX9691L

SINGLE CHIP SOLID STATE DISK CONTROLLER

Macronix International 

MX9691L

4. PIN DESCRIPTION

Host Interface

Symbol

HA[10:0]

HD[15:0]

HOE#,HWE#

No.

92,94,

96-97,99

101-103,

106,109,

113

84-89,

116-117,

121-128

104,111

IOR#,IOW#

107,110

HRESET/HRESET# 100

WAIT/ IOCHRDY

98

RDY/BSY#/

119

IREQ#/

HOSTINT

Type

I

(CMOS)

I/O

(TTL)

I

(CMOS)

I

(CMOS)

I

(CMOS)

O,OD

(CMOS)

O, Z

(CMOS)

Description

Host address line 10-0.

These pins include internal pull-up resistors.

Host data line 15-0.

These pins include internal bus holder circuit that keep

previous state when tri-state.

Host memory read/write/mode select :

Both pins include internal pull-up resistors that is default in

PCMCIA mode.

Host I/O access.

Both pins include internal pull-up resistor.

The host reset signal, when active, initializes the control/

status registers and stops any command in process.

In PCMCIA mode, the signal is active high.

In True IDE mode, this signal is active low.

This signal include internal pull-down resistor.

WAIT or INPUT CHANNEL READY : In both PCMCIA and

True IDE modes, this signal holds host transfers until the

controller is ready to respond.

READY/BUSY or HOST INTERRUPT : In PCMCIA mode,

this signal has two functions. In PCMCIA common memory

mode, this signal is ready/busy. It is asserted busy by the

reset logic, and can be deasserted by the DSP or

represents the ready/busy bit of ATA status register.

In PCMCIA I/O mode, this signal is IREQ#.

In True IDE mode, this active high signal is HOSTINT, which,

when enable, send an interrupt to the host.

P/N:PM0546

REV. 1.1, JUL. 02, 1999

4

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