AD73311L Ver la hoja de datos (PDF) - Analog Devices
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AD73311L Datasheet PDF : 36 Pages
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AD73311L
Parameter
VREFCAP
VREFOUT
ADC
DAC
Condition
Table II. Signal Ranges
Maximum Input Range at VIN
Nominal Reference Level
Maximum Voltage
Output Swing
Single-Ended
Differential
Nominal Voltage
Output Swing
Single-Ended
Differential
Output Bias Voltage
Signal Range
1.2 V ± 10%
1.2 V ± 10%
1.578 V p-p
1.0954 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
VREFOUT
TIMING CHARACTERISTICS (AVDD = DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted)
Parameter
Limit at
TA = –40؇C to +105؇C
Unit
Description
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
t1
t2
t3
Figure 1. MCLK Timing
100A IOL
TO OUTPUT
PIN
CL
15pF
100A IOH
2.1V
Figure 2. Load Circuit for Timing Specifications
MCLK
SCLK*
t1
t2
t3
t13
t5
t6
t4
*SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
–4–
REV. A
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