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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

Write TX FIFO Data Port Register : WRTXFIFOD[31:0] ( reg 4B-48h ), WO

Bit

48.7-0,

49.7-0

4A.7-0

4B.7-0

Symbol

WRTXFIFOD[31:0]

Description

Write TX FIFO Data Port : The 32 bit write only data port for the TX on-chip

FIFO in the direct FIFO mode. In the 32 bit mode, H16_32=0, the MSB byte

(byte 3) is Reg4Bh and the LSB byte (Byte 0) is Reg48h. In the 16 bit

mode, H16_32=1, Reg49h is the MSB byte (byte 1) and Reg48h is the LSB

byte (byte 0). An internal counter (TXFIFOBC) is used to keep track of the

total number of bytes written to the FIFO through this port before the host

issues reg00h.ST1=1, ST0=0 (the TX FIFO send command). Do not write

to this port when the TX local DMA is still active.

IO Read Data Port Register : IORD[31:0] ( reg 4C-4Fh ), RO

4C.7-0,

4D.7-0

4E.7-0

4F.7-0

IORD[31:0]

IO Read Data Port : The 32 bit read only data port that works with the

IORDP page pointer. In the 32 bit mode, H16_32=0, the MSB byte (byte 3)

is Reg4Fh and the LSB byte (byte 0) is Reg4Ch. In the 16 bit mode,

H16_32=1, Reg4Dh is the MSB byte (byte 1) and Reg4Ch is the LSB byte

(byte 0). An internal counter (IORDPBC) is used to keep track of the

current location within a particular page . For the system that does not

support the SRDY pin, the Register 3A.1 bit (STIORD/RRDYB ) can be

used to read this port in a hand shaking manner. To use register 3A.1 ,first

write 1 to register 3A.1. When the data is ready in this IORD port, register

3A.1 bit will be internally cleared to 0. So the host can read the register

3A.1 bit for 0 in order to know whether the data is ready or not. This IORD

can be used to fetch TX descriptors in a multiple packets send operation.

P/N:PM0723

REV. 1.0, JUL. 13, 2000

25

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