M30802FG Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
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M30802FG Datasheet PDF : 315 Pages
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Udnedveerlopment
Preliminary Specifications REV.B
Specifications in this manual are tentative
Pin Description
and
subject
to
change.
M16C/80
SINGLE-CHIP
Mitsubishi microcomputers
(144-pin version) group
16-BIT CMOS MICROCOMPUTER
Pin Description
Pin name
P40 to P47
A16 to A22,
A23
CS0 to CS3
Signal name
I/O port P4
MA8 to MA12
P50 to P57 I/O port P5
I/O type
Input/output
Output
Output
Output
Input/output
Function
This is an 8-bit I/O port equivalent to P0.
These pins output 8 high-order address bits (A16–A22, A23). Highest
address bit (A23) outputs inversely.
These pins output CS0–CS3 signals. CS0–CS3 are chip select signals
used to specify an access space.
If accessing to DRAM area, these pins output data separated in time by
multiplexing.
This is an 8-bit I/O port equivalent to P0. P53 in this port outputs a
divide-by-8 or divide-by-32 clock of XIN or a clock of the same
frequency as XCIN as selected by software.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
DW,
CASL,
CASH,
RAS
Output
Output
Output
Output
Output
Input
Output
Input
Output
Output
Output
Output
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
When accessing to DRAM area while DW signal is “L”, write to DRAM.
CASL and CASH show timing when latching to line address. When
CASL accesses to even address, and CASH to odd, these two pins
become “L”. RAS signal shows timing when latching to row address.
P60 to P67 I/O port P6
Input/output
This is an 8-bit I/O port equivalent to P0. When set for input in single
chip mode, the user can specify in units of four bits via software
whether or not they are tied to a pull-up resistance. In memory
expansion and microprocessor mode, an built-in pull-up resistance
cannot be used. Pins in this port also function as UART0 and UART1 I/
O pins as selected by software.
P70 to P77 I/O port P7
Input/output
This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N-channel
open drain output). Pins in this port also function as timer A0–A3,
timer B5 or UART2 I/O pins as selected by software.
P80 to P84,
P86,
P87,
P85
I/O port P8
I/O port P85
Input/output
Input/output
Input/output
Input
P80 to P84, P86, and P87 are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P86 and P87 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P86 (XCOUT
pin) and P87 (XCIN pin). P85 is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be canceled using
software. The pull-up cannot be set for this pin.
P90 to P97 I/O port P9
P100 to P107 I/O port P10
Input/output
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as UART3 and UART4 I/O pins, Timer B0–B4 input pins, D-A converter
output pins, A-D converter extended input pins, or A-D trigger input pins
as selected by software.
Input/output
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. Furthermore, P104–P107 also function as
input pins for the key input interrupt function.
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