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BT848AKPF

Single-Chip Video Capture for PCI

Conexant Systems 

FUNCTIONAL DESCRIPTION

Functional Overview

Figure 2. Bt848 Video Decoder and Scaler Block Diagram

Bt848/848A/849A

Single-Chip Video Capture for PCI

YREF+

YIN

YREF–

Clocking

CLEVEL

CREF+

CIN

CREF–

Notes: (1). Bt848 only.

(2). Bt848A and Bt849A only.

PCI Bus Interface

Bt848/848A/849A is designed to efficiently utilize the available 132 MB/s PCI

bus. The 32-bit DWORDs are output on the PCI bus with the appropriate image

data under the control of the DMA channels. The video stream consumes bus

bandwidth with average data rates varying from 44 MB/s for full size 768x576

PAL RGB32, to 4.6 MB/s for NTSC CIF 320 x 240 RGB16, to 0.14 MB/s for

NTSC ICON 80 x 60 8-bit mode.

The pixel instruction stream for the DMA channels consumes a minimum of 0.1

MB/s. Achieving high performance throughput on PCI may be a problem with

slow targets and long bus access latencies. The Bt848/848A/849A provides the

means for handling the bandwidth bottlenecks that sometimes occur depending on

a particular system configuration. Bt848/848A/849A’s ability to gracefully de-

grade and to recover from FIFO overruns to the nearest pixel in real-time is the best

possible solution to these system bottlenecks.

4

L848A_A

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