AD7723BSZ-REEL Ver la hoja de datos (PDF) - Analog Devices
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AD7723BSZ-REEL Datasheet PDF : 32 Pages
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AD7723
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V ± 5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT = logic low or high, CFMT = logic low
or high; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
CLKIN Frequency
CLKIN Period (tCLK – 1/fCLK)
CLKIN Low Pulse Width
CLKIN High Pulse Width
CLKIN Rise Time
CLKIN Fall Time
FSI Setup Time
FSI Hold Time
FSI High Time1
CLKIN to SCO Delay
SCO Period2, SCR = 1
SCO Period2, SCR = 0
SCO Transition to FSO High Delay
SCO Transition to FSO Low Delay
SCO Transition to SDO Valid Delay
SCO Transition from FSI3
SDO Enable Delay Time
SDO Disable Delay Time
DRDY High Time2
Conversion Time2 (Refer to Table 3 and Table 4)
CLKIN to DRDY Transition
CLKIN to DATA Valid
CS/RD Setup Time to CLKIN
CS/RD Hold Time to CLKIN
Data Access Time
Bus Relinquish Time
SYNC Input Pulse Width
SYNC Low Time before CLKIN Rising
DRDY High Delay after Rising SYNC
DRDY Low Delay after SYNC Low
Symbol
fCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
Min
1
0.052
0.45 × t1
0.45 × t1
5
5
0
0
2
16/32
0
20
1
0
Typ Max
19.2
1
0.55 × t1
0.55 × t1
5
5
1
25
40
2
1
0
5
0
5
5
12
60
tCLK + t2
5
20
5
20
35
50
20
35
20
35
20
35
25
35
2049
Unit
MHz
µs
ns
ns
ns
ns
tCLK
ns
tCLK
tCLK
ns
ns
ns
ns
ns
tCLK
tCLK
ns
ns
ns
ns
ns
ns
tCLK
ns
ns
tCLK
1 FSO pulses are gated by the release of FSI (going low).
2 Guaranteed by design.
3 Frame sync is initiated on the falling edge of CLKIN.
IOL
1.6mA
TO
OUTPUT
PIN CL
50pF
1.6V
IOH
200µA
Figure 2. Load Circuit for Timing Specifications
Rev. C | Page 6 of 32
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